Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84585?usp=email )
Change subject: nb/intel/*: Explicitly include static.h for config_of_soc ......................................................................
nb/intel/*: Explicitly include static.h for config_of_soc
As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h.
Change-Id: Iac8063d2021af83203be8a10b2962c9fb3dd106a Signed-off-by: Nicholas Chin nic.c3.14@gmail.com --- M src/northbridge/intel/haswell/broadwell_mrc/raminit.c M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/northbridge/intel/haswell/native_raminit/raminit_main.c M src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c A src/northbridge/intel/sandybridge/early_gma.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/raminit_native.c 8 files changed, 101 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/84585/1
diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c index 1ed42485..beae496 100644 --- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c @@ -20,6 +20,7 @@ #include <northbridge/intel/haswell/raminit.h> #include <smbios.h> #include <spd.h> +#include <static.h> #include <security/vboot/vboot_common.h> #include <commonlib/region.h> #include <southbridge/intel/lynxpoint/me.h> diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index 9a7b7fe..3d5e46c 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -18,6 +18,7 @@ #include <northbridge/intel/haswell/raminit.h> #include <smbios.h> #include <spd.h> +#include <static.h> #include <security/vboot/vboot_common.h> #include <commonlib/region.h> #include <southbridge/intel/lynxpoint/me.h> diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c index 19ec585..2271705 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c @@ -7,6 +7,7 @@ #include <northbridge/intel/haswell/chip.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> +#include <static.h> #include <string.h> #include <types.h>
diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c index c53ea12..a422591 100644 --- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c +++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c @@ -8,6 +8,7 @@ #include <northbridge/intel/haswell/chip.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> +#include <static.h> #include <string.h> #include <types.h>
diff --git a/src/northbridge/intel/sandybridge/early_gma.c b/src/northbridge/intel/sandybridge/early_gma.c new file mode 100644 index 0000000..30da5ed --- /dev/null +++ b/src/northbridge/intel/sandybridge/early_gma.c @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <device/mmio.h> +#include <console/console.h> +#include <bootmode.h> +#include <cpu/intel/model_206ax/model_206ax.h> +#include <delay.h> +#include <device/device.h> +#include <static.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <drivers/intel/gma/libgfxinit.h> +#include <drivers/intel/gma/opregion.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <static.h> +#include <types.h> +#include <cpu/x86/mtrr.h> + +#include "chip.h" +#include "sandybridge.h" +#include "early_graphics.h" + +static struct resource *gtt_res = NULL; + +static struct resource early_gtt_res = { + .base = CONFIG_GFX_GMA_DEFAULT_MMIO +}; + +static u32 early_gtt_read(u32 reg) +{ + void *p = res2mmio(gtt_res, reg, 0); + printk(BIOS_DEBUG, "gtt_read(%p)\n", p); + return read32(p); +} + +static void early_gtt_write(u32 reg, u32 data) +{ + void *p = res2mmio(gtt_res, reg, 0); + printk(BIOS_DEBUG, "gtt_write(%p, 0x%08x)\n", p, data); + write32(p, data); +} + +void early_graphics_panel_init(void) +{ + pci_devfn_t host_bridge = PCI_DEV(0, 0, 0); + printk(BIOS_DEBUG, "Host Bridge DEVEN: 0x%04x\n", pci_read_config32(host_bridge, 0x54)); + display_mtrrs(); + gtt_res = &early_gtt_res; + const struct northbridge_intel_sandybridge_config *conf = config_of_soc(); + u32 reg32; + + /* Setup Panel Power On Delays */ + printk(BIOS_DEBUG, "Setup Panel Power On Delays\n"); + reg32 = early_gtt_read(0xc7208); + if (!reg32) { + reg32 = (conf->gpu_panel_port_select & 0x3) << 30; + reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + early_gtt_write(0xc7208, reg32); + } + + /* Setup Panel Power Off Delays */ + printk(BIOS_DEBUG, "Setup Panel Power Off Delays\n"); + reg32 = early_gtt_read(0xc720c); + if (!reg32) { + reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + early_gtt_write(0xc720c, reg32); + } + + /* Setup Panel Power Cycle Delay */ + printk(BIOS_DEBUG, "Setup Panel Power Cycle Delay\n"); + if (conf->gpu_panel_power_cycle_delay) { + reg32 = early_gtt_read(0xc7210); + reg32 &= ~0xff; + reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; + early_gtt_write(0xc7210, reg32); + } + + /* Enable Backlight if needed */ + printk(BIOS_DEBUG, "Enable Backlight\n"); + if (conf->gpu_cpu_backlight) { + early_gtt_write(0x48250, (1 << 31)); + early_gtt_write(0x48254, conf->gpu_cpu_backlight); + } + if (conf->gpu_pch_backlight) { + early_gtt_write(0xc8250, (1 << 31)); + early_gtt_write(0xc8254, conf->gpu_pch_backlight); + } +} diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index d5e1a7c..9ec8fb6f 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -15,6 +15,7 @@ #include <mrc_cache.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <static.h> #include <cpu/x86/msr.h> #include <types.h>
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 98b3028..b81716a 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -19,6 +19,7 @@ #include <mrc_cache.h> #include <spd.h> #include <smbios.h> +#include <static.h> #include <stddef.h> #include <stdint.h> #include <timestamp.h> diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index ecae91b..ed11945 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -9,6 +9,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <northbridge/intel/sandybridge/chip.h> +#include <static.h> #include <stdbool.h> #include <stdint.h>
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Nicholas Chin (Code Review)