Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration

[Subrata Banik (Code Review)]

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan.
Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan, Werner Zeh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/63630

to look at the new patch set (#2).

Change subject: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
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soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration

This patch implements a helper function to perform LPC registers lock
down configuration.

BUG=b:211954778
TEST=Able to build and boot google/redrix to OS. Verified LPC PCI
configuration register offset 0xDC bits BILD and LE are set.

Signed-off-by: Subrata Banik 
Change-Id: I3e49b783e5db0ff40238e6e9259e48a4ecca66f8
---
M src/soc/intel/common/pch/lockdown/lockdown.c
1 file changed, 20 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/63630/2