HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45639 )
Change subject: northbridge/intel: Use common 'MCHBARx()' ......................................................................
northbridge/intel: Use common 'MCHBARx()'
Change-Id: I67cb587c51f706eeb1e47dda83ece8b403ef7738 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/i945/i945.h M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/sandybridge/sandybridge.h M src/northbridge/intel/x4x/x4x.h 7 files changed, 9 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/45639/1
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 8196e90..4f9d82f 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -3,6 +3,7 @@ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ #define __NORTHBRIDGE_INTEL_GM45_GM45_H__
+#include <northbridge/intel/common/mchbar_ops.h> #include <southbridge/intel/i82801ix/i82801ix.h>
#ifndef __ACPI__ @@ -237,10 +238,6 @@ * MCHBAR */
-#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) - #define HPLLVCO_MCHBAR 0x0c0f
#define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 4bcaaa7..b7328e7 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -10,6 +10,7 @@
#include "memmap.h"
+#include <northbridge/intel/common/mchbar_ops.h> #include <southbridge/intel/lynxpoint/pch.h>
/* Everything below this line is ignored in the DSDT */ @@ -28,9 +29,6 @@ * MCHBAR */
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 26fc931..365c7b9 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -14,6 +14,7 @@ #endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
+#include <northbridge/intel/common/mchbar_ops.h> #include <southbridge/intel/i82801gx/i82801gx.h>
/* Everything below this line is ignored in the DSDT */ @@ -99,10 +100,6 @@ * MCHBAR */
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) - /* Chipset Control Registers */ #define FSBPMC3 0x40 /* 32bit */ #define FSBPMC4 0x44 /* 32bit */ diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 97a9391..4da9854 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -3,6 +3,8 @@ #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ #define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__
+#include <northbridge/intel/common/mchbar_ops.h> + #define DEFAULT_HECIBAR ((u8 *)0xfed17000)
#define IOMMU_BASE1 0xfed90000 @@ -100,9 +102,6 @@ * MCHBAR */
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 03fa318..aecf2ac 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -3,6 +3,7 @@ #ifndef NORTHBRIDGE_INTEL_PINEVIEW_H #define NORTHBRIDGE_INTEL_PINEVIEW_H
+#include <northbridge/intel/common/mchbar_ops.h> #include <northbridge/intel/pineview/memmap.h> #include <southbridge/intel/i82801gx/i82801gx.h>
@@ -38,9 +39,6 @@ * MCHBAR */
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) /* FIXME: causes changes */ #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 8f9d118..853c8f8 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -3,6 +3,8 @@ #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
+#include <northbridge/intel/common/mchbar_ops.h> + /* Device ID for SandyBridge and IvyBridge */ #define BASE_REV_SNB 0x00 #define BASE_REV_IVB 0x50 @@ -49,9 +51,6 @@ * MCHBAR */
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 45785a0..84ee6bb 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -3,6 +3,7 @@ #ifndef __NORTHBRIDGE_INTEL_X4X_H__ #define __NORTHBRIDGE_INTEL_X4X_H__
+#include <northbridge/intel/common/mchbar_ops.h> #include <stdint.h> #include "iomap.h"
@@ -40,9 +41,6 @@ * MCHBAR */
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) #define MCHBAR8_AND_OR(x, and, or) \
Hello build bot (Jenkins), Damien Zammit, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45639
to look at the new patch set (#2).
Change subject: northbridge/intel: Use common 'MCHBARx()' ......................................................................
northbridge/intel: Use common 'MCHBARx()'
Change-Id: I67cb587c51f706eeb1e47dda83ece8b403ef7738 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/i945/i945.h M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/sandybridge/sandybridge.h M src/northbridge/intel/x4x/x4x.h 7 files changed, 8 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/45639/2
Hello build bot (Jenkins), Damien Zammit, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45639
to look at the new patch set (#4).
Change subject: northbridge/intel: Use common MCHBARx(), DMIBARx() and EPBARx() ......................................................................
northbridge/intel: Use common MCHBARx(), DMIBARx() and EPBARx()
Change-Id: I67cb587c51f706eeb1e47dda83ece8b403ef7738 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/i945/i945.h M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/sandybridge/sandybridge.h M src/northbridge/intel/x4x/x4x.h 7 files changed, 8 insertions(+), 107 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/45639/4
Hello build bot (Jenkins), Damien Zammit, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45639
to look at the new patch set (#7).
Change subject: northbridge/intel: Use common MCHBARx(), DMIBARx() and EPBARx() ......................................................................
northbridge/intel: Use common MCHBARx(), DMIBARx() and EPBARx()
Change-Id: I67cb587c51f706eeb1e47dda83ece8b403ef7738 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/i945/i945.h M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/sandybridge/sandybridge.h M src/northbridge/intel/x4x/x4x.h 7 files changed, 26 insertions(+), 99 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/45639/7
Hello build bot (Jenkins), Damien Zammit, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45639
to look at the new patch set (#8).
Change subject: northbridge/intel: Use common MCHBARx(), DMIBARx() and EPBARx() ......................................................................
northbridge/intel: Use common MCHBARx(), DMIBARx() and EPBARx()
Change-Id: I67cb587c51f706eeb1e47dda83ece8b403ef7738 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/i945/i945.h M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/sandybridge/sandybridge.h M src/northbridge/intel/x4x/x4x.h 7 files changed, 8 insertions(+), 107 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/45639/8
Hello build bot (Jenkins), Damien Zammit, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45639
to look at the new patch set (#10).
Change subject: northbridge/intel: Use common MCHBARx(), DMIBARx() and EPBARx() ......................................................................
northbridge/intel: Use common MCHBARx(), DMIBARx() and EPBARx()
Change-Id: I67cb587c51f706eeb1e47dda83ece8b403ef7738 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/i945/i945.h M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/sandybridge/sandybridge.h M src/northbridge/intel/x4x/x4x.h 7 files changed, 8 insertions(+), 107 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/45639/10
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45639 )
Change subject: northbridge/intel: Use common MCHBARx(), DMIBARx() and EPBARx() ......................................................................
Abandoned
-
HAOUAS Elyes (Code Review)