Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52060 )
Change subject: soc/intel/xeon_sp: More PCU locks ......................................................................
soc/intel/xeon_sp: More PCU locks
Add the following locks as recommended by the Intel docs:
DRAM_POWER_INFO_LOCK PCU_CR3_FLEX_RATIO_LOCK TURBO_ACTIVATION_RATIO_LOCK PCU_CR0_PMAX_LOCK
Change-Id: I8d8211977e87109a91790a4070454fc561aa761b Signed-off-by: Marc Jones marcjones@sysproconsulting.com --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/util.c 4 files changed, 28 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/52060/1
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index a223542..500f83e 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -121,6 +121,8 @@ const struct device *cr0_dev = PCU_DEV_CR0(bus); pci_or_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); pci_or_config32(cr0_dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, PKG_PWR_LIM_LOCK_UPR); + pci_or_config32(cr0_dev, PCU_CR0_TURBO_ACTIVATION_RATIO, TURBO_ACTIVATION_RATIO_LOCK); +
/* configure PCU_CR1_FUN csrs */ const struct device *cr1_dev = PCU_DEV_CR1(bus); @@ -129,10 +131,12 @@ /* configure PCU_CR2_FUN csrs */ const struct device *cr2_dev = PCU_DEV_CR2(bus); pci_or_config32(cr2_dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT, PP_PWR_LIM_LOCK); + pci_or_config32(cr2_dev, PCU_CR2_DRAM_POWER_INFO_UPR, DRAM_POWER_INFO_LOCK_UPR);
/* configure PCU_CR3_FUN csrs */ const struct device *cr3_dev = PCU_DEV_CR3(bus); pci_or_config32(cr3_dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); + pci_or_config32(cr3_dev, PCU_CR3_FLEX_RATIO, OC_LOCK); }
} diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 122a376..7b16945 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -25,11 +25,15 @@ #define PCU_CR0_FUN 0 #define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 +#define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 +#define TURBO_ACTIVATION_RATIO_LOCK BIT(31) #define PCU_CR0_P_STATE_LIMITS 0xd8 -#define P_STATE_LIMITS_LOCK BIT(31) +#define P_STATE_LIMITS_LOCK BIT(31) #define PCU_CR0_PACKAGE_RAPL_LIMIT_LWR 0xe8 #define PCU_CR0_PACKAGE_RAPL_LIMIT_UPR (PCU_CR0_PACKAGE_RAPL_LIMIT_LWR + 4) -#define PKG_PWR_LIM_LOCK_UPR BIT(31) +#define PKG_PWR_LIM_LOCK_UPR BIT(31) +#define PCU_CR0_PMAX 0xf0 +#define PMAX_LOCK BIT(31)
#define PCU_CR1_FUN 1 #define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN) @@ -60,13 +64,18 @@
#define PCU_CR2_FUN 2 #define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) +#define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 +#define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) +#define DRAM_POWER_INFO_LOCK_UPR BIT(31) #define PCU_CR2_DRAM_PLANE_POWER_LIMIT 0xf0 #define PP_PWR_LIM_LOCK BIT(31)
#define PCU_CR3_FUN 3 #define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) #define PCU_CR3_CONFIG_TDP_CONTROL 0x60 -#define TDP_LOCK BIT(31) +#define TDP_LOCK BIT(31) +#define PCU_CR3_FLEX_RATIO 0xa0 +#define OC_LOCK BIT(20)
#if !defined(__SIMPLE_DEVICE__) #define _UBOX_DEV(func) pcidev_path_on_root_debug(PCI_DEVFN(UBOX_DEV, func), __func__) diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index c7af810..96239ba 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -26,11 +26,18 @@ #define SAD_ALL_PAM0123_CSR 0x40 #define SAD_ALL_PAM456_CSR 0x44
+#if !defined(__SIMPLE_DEVICE__) +#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) +#else +#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func) +#endif + #define PCU_IIO_STACK 1 #define PCU_DEV 30 #define PCU_CR1_FUN 1
#define PCU_CR0_FUN 0 +#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_P_STATE_LIMITS 0xd8 #define P_STATE_LIMITS_LOCK_SHIFT 31 @@ -40,6 +47,8 @@ #define PCU_CR0_CURRENT_CONFIG 0xf8 #define MAX_NON_TURBO_LIM_RATIO_SHIFT 8 /* 8:15 */ #define MAX_NON_TURBO_LIM_RATIO_MASK (0xff << MAX_NON_TURBO_LIM_RATIO_SHIFT) +#define PCU_CR0_PMAX 0xf0 +#define PMAX_LOCK BIT(31)
#define PCU_CR1_BIOS_MB_DATA_REG 0x8c
diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index baf5102..ce0b1a6 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -318,6 +318,9 @@ if (timedout) die("BIOS RESET CPL3 timed out.\n");
+ /* Set PMAX_LOCK - must be set before RESET CPL4 */ + pci_or_config32(PCU_DEV_CR0(bus), PCU_CR0_PMAX, PMAX_LOCK); + /* update RST_CPL4, PCODE_INIT_DONE4 */ timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK, PCODE_INIT_DONE4_MASK, RST_CPL4_MASK);
-
Marc Jones (Code Review)