Werner Zeh (werner.zeh@siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709
-gerrit
commit 66049bcb2ba5b65f59d93fa6d00b0792249af15c Author: Werner Zeh werner.zeh@siemens.com Date: Fri Sep 25 07:54:59 2015 +0200
intel/fsp1.0: Get size of microcode during build time
Avoid specifying the size of the microcode in microcode_size.h. Instead, the size will be determined during build time and microcode_size.h will be generated. This way, the size does not need to be adjusted by hand.
Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502 Signed-off-by: Werner Zeh werner.zeh@siemens.com --- src/drivers/intel/fsp1_0/Makefile.inc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index 11ff31a..7e970c1 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -23,8 +23,9 @@ romstage-y += fsp_util.c hob.c ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 +CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
+cpu_incs-$(CONFIG_PLATFORM_USES_FSP1_0) += $(objgenerated)/microcode_size.h cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
ifeq ($(CONFIG_HAVE_FSP_BIN),y) @@ -45,3 +46,8 @@ mrc.cache-file := $(obj)/mrc.cache mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache endif + +$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin + printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp \ + && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@ +
-
Werner Zeh