[L] Change in coreboot[main]: mainboard/lenovo: Add ThinkCentre M710s (Skylake)

[Felix Singer (Code Review)]

Attention is currently required from: Nicholas Sudsgaard.

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80343?usp=email )

Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
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Patch Set 27:

(1 comment)

File src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/80343/comment/bc2efcec_7049170d :
PS27, Line 12: register "PcieRpClkReqSupport[0]" = "true"
             : 			register "PcieRpClkReqNumber[0]"  = "2"
             : 			register "PcieRpClkSrcNumber[0]"  = "0"
> Uh, this is a CPU RP, not a PCH RP. I'm pretty sure the CPU RP UPDs aren't exposed as devicetree settings on Skylake.

Oh, right! I didn't expand the Gerrit view and so I only saw the option names.

I think you are right. I also couldn't find any similar UPDs for the CPU root ports.