Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/28939
Change subject: soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled ......................................................................
soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled
This change sets PCIEXPWAK_DIS in PM1_EN register if WAKE# pin is not enabled on the platform. This is required to prevent unnecessary wakes if the WAKE# pin remains not connected on the platform.
BUG=b:117284700 TEST=Verified that no spurious wakes are observed on nocturne.
Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/skylake/cpu.c 1 file changed, 13 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/28939/1
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 417c4bc..925b694 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -466,14 +466,26 @@
static void post_mp_init(void) { + struct device *dev = SA_DEV_ROOT; + config_t *conf; + uint16_t pm1_en = GBL_EN; + /* Set Max Ratio */ cpu_set_max_ratio();
+ if (dev && dev->chip_info) { + conf = dev->chip_info; + if (!(conf->deep_sx_config & DSX_EN_WAKE_PIN)) { + printk(BIOS_INFO, "Setting PCI Express Wake Disable.\n"); + pm1_en |= PCIEXPWAK_DIS; + } + } + /* * Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ - smm_southbridge_enable(GBL_EN); + smm_southbridge_enable(pm1_en);
/* Lock down the SMRAM space. */ #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)