New subject: Change in coreboot[master]: mediatek/mt8183: Add I2C driver code

17 Jan 2019

wang qii has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30976
Change subject: mediatek/mt8183: Add I2C driver code
......................................................................
mediatek/mt8183: Add I2C driver code
This patch implements i2c driver for MT8183.
BUG=b:80501386
BRANCH=none
TEST=Boot correctly on kukui.
Change-Id: I0a4d78b494819f45951f78e5a618021000cf3463
Signed-off-by: qii wang qii.wang@mediatek.com
---
M src/soc/mediatek/mt8183/Makefile.inc
A src/soc/mediatek/mt8183/i2c.c
M src/soc/mediatek/mt8183/include/soc/addressmap.h
A src/soc/mediatek/mt8183/include/soc/i2c.h
4 files changed, 236 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/30976/1

diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
index 9aa1733..b0a148f 100644
--- a/src/soc/mediatek/mt8183/Makefile.inc
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -5,6 +5,7 @@
 bootblock-y += ../common/gpio.c gpio.c
 bootblock-y += ../common/pll.c pll.c
 bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
+bootblock-y += ../common/i2c.c i2c.c
 bootblock-y += ../common/timer.c
 bootblock-y += ../common/uart.c
 bootblock-y += ../common/wdt.c
@@ -16,6 +17,7 @@
 verstage-y += auxadc.c
 verstage-y += ../common/gpio.c gpio.c
 verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
+verstage-y += ../common/i2c.c i2c.c
 verstage-y += ../common/timer.c
 verstage-y += ../common/uart.c
 verstage-y += ../common/wdt.c
@@ -31,6 +33,7 @@
 romstage-y += ../common/mmu_operations.c mmu_operations.c
 romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
+romstage-y += ../common/i2c.c i2c.c
 romstage-y += ../common/timer.c
 romstage-y += ../common/uart.c
 romstage-y += ../common/wdt.c
@@ -42,6 +45,7 @@
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += soc.c
 ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
+ramstage-y += ../common/i2c.c i2c.c
 ramstage-y += ../common/timer.c
 ramstage-y += ../common/uart.c
 ramstage-y += ../common/usb.c
diff --git a/src/soc/mediatek/mt8183/i2c.c b/src/soc/mediatek/mt8183/i2c.c
new file mode 100644
index 0000000..f389caf
--- /dev/null
+++ b/src/soc/mediatek/mt8183/i2c.c
@@ -0,0 +1,171 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <arch/io.h>
+#include <soc/pll.h>
+#include <soc/i2c.h>
+#include <soc/gpio.h>
+
+#define I2C_CLK_HZ (UNIVPLL_HZ / 30)
+
+struct mtk_i2c mtk_i2c_bus_controller[] = {
+	/* i2c0 setting */
+	{
+		.i2c_regs = (void *)(I2C_BASE + 0x2000),
+		.i2c_dma_regs = (void *)(I2C_DMA_BASE),
+	},
+
+	/* i2c1 setting */
+	{
+		.i2c_regs = (void *)(I2C_BASE + 0xc000),
+		.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x400),
+	},
+
+	/* i2c2 setting */
+	{
+		.i2c_regs = (void *)(I2C_BASE + 0x4000),
+		.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x200),
+	},
+
+	/* i2c3 setting */
+	{
+		.i2c_regs = (void *)(I2C_BASE + 0xa000),
+		.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x380),
+	},
+
+	/* i2c4 setting */
+	{
+		.i2c_regs = (void *)(I2C_BASE + 0x3000),
+		.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x80),
+	},
+
+	/* i2c5 setting */
+	{
+		.i2c_regs = (void *)(I2C_BASE + 0x11000),
+		.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x480),
+	},
+
+	/* i2c6 setting */
+	{
+		.i2c_regs = (void *)(I2C_BASE),
+		.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x580),
+	},
+
+	/* i2c7 setting */
+	{
+		.i2c_regs = (void *)(I2C_BASE + 0x15000),
+		.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x600),
+	},
+
+	/* i2c8 setting */
+	{
+		.i2c_regs = (void *)(I2C_BASE + 0x16000),
+		.i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x680),
+	}
+};
+
+#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller)
+
+struct pad_func {
+	gpio_t gpio;
+	u8 func;
+};
+
+#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func}
+
+static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = {
+	{
+		PAD_FUNC(SDA0, SDA0),
+		PAD_FUNC(SCL0, SCL0),
+	},
+	{
+		PAD_FUNC(SDA1, SDA1),
+		PAD_FUNC(SCL1, SCL1),
+	},
+	{
+		PAD_FUNC(SDA2, SDA2),
+		PAD_FUNC(SCL2, SCL2),
+	},
+	{
+		PAD_FUNC(SDA3, SDA3),
+		PAD_FUNC(SCL3, SCL3),
+	},
+	{
+		PAD_FUNC(SDA4, SDA4),
+		PAD_FUNC(SCL4, SCL4),
+	},
+	{
+		PAD_FUNC(SDA5, SDA5),
+		PAD_FUNC(SCL5, SCL5),
+	},
+	{
+		PAD_FUNC(CONN_TOP_DATA, SDA6),
+		PAD_FUNC(CONN_TOP_CLK, SCL6),
+	},
+	{
+	},
+	{
+		PAD_FUNC(CAM_RST2, SDA8),
+		PAD_FUNC(CAM_CLK2, SCL8),
+	},
+};
+
+static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
+{
+	assert(bus < I2C_BUS_NUMBER && bus != 7);
+
+	const struct pad_func *ptr = i2c_funcs[bus];
+	for (size_t i = 0; i < 2; i++) {
+		gpio_set_mode(ptr[i].gpio, ptr[i].func);
+		gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP);
+		if (bus < 6) {
+			gpio_set_i2c_eh(ptr[i].gpio, 0);
+			gpio_set_i2c_rsel(ptr[i].gpio, 3);
+		}
+	}
+}
+
+static void mtk_i2c_speed_init(uint8_t bus)
+{
+	uint8_t step_div;
+	const uint8_t clock_div = 5;
+	const uint8_t sample_div = 1;
+	uint32_t i2c_freq;
+
+	assert(bus < ARRAY_SIZE(mtk_i2c_bus_controller));
+
+	/* Calculate i2c frequency */
+	step_div = DIV_ROUND_UP(I2C_CLK_HZ,
+				(400 * KHz * sample_div * 2) * clock_div);
+	i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div);
+	assert(sample_div < 8 && step_div < 64 && i2c_freq <= 400 * KHz &&
+	       i2c_freq >= 380 * KHz);
+
+	/* Init i2c bus Timing register */
+	write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing,
+		(sample_div - 1) << 8 | (step_div - 1));
+	write32(&mtk_i2c_bus_controller[bus].i2c_regs->ltiming,
+		(sample_div - 1) << 6 | (step_div - 1));
+
+	/* Init i2c bus clock_div register */
+	write32(&mtk_i2c_bus_controller[bus].i2c_regs->clock_div, clock_div - 1);
+}
+
+void mtk_i2c_init(uint8_t bus)
+{
+	mtk_i2c_speed_init(bus);
+	mtk_i2c_set_gpio_pinmux(bus);
+}
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index d41b2b9..aaa77a3 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -34,8 +34,10 @@
    EMI_BASE		= IO_PHYS + 0x00219000,
    EMI_MPU_BASE		= IO_PHYS + 0x00226000,
    DRAMC_CH_BASE		= IO_PHYS + 0x00228000,
+	I2C_DMA_BASE		= IO_PHYS + 0x01000080,
    AUXADC_BASE		= IO_PHYS + 0x01001000,
    UART0_BASE		= IO_PHYS + 0x01002000,
+	I2C_BASE		= IO_PHYS + 0x01005000,
    SPI0_BASE		= IO_PHYS + 0x0100A000,
    SPI1_BASE		= IO_PHYS + 0x01010000,
    SPI2_BASE		= IO_PHYS + 0x01012000,
diff --git a/src/soc/mediatek/mt8183/include/soc/i2c.h b/src/soc/mediatek/mt8183/include/soc/i2c.h
new file mode 100755
index 0000000..dbf9cbf
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/i2c.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_MEDIATEK_MT8183_I2C_H
+#define SOC_MEDIATEK_MT8183_I2C_H
+
+#include <soc/i2c_common.h>
+
+/* I2C Register */
+struct mt_i2c_regs {
+	uint32_t data_port;
+	uint32_t slave_addr;
+	uint32_t intr_mask;
+	uint32_t intr_stat;
+	uint32_t control;
+	uint32_t transfer_len;
+	uint32_t transac_len;
+	uint32_t delay_len;
+	uint32_t timing;
+	uint32_t start;
+	uint32_t ext_conf;
+	uint32_t ltiming;
+	uint32_t hs;
+	uint32_t io_config;
+	uint32_t fifo_addr_clr;
+	uint32_t reserved0[2];
+	uint32_t transfer_aux_len;
+	uint32_t clock_div;
+	uint32_t time_out;
+	uint32_t softreset;
+	uint32_t reserved1[36];
+	uint32_t debug_stat;
+	uint32_t debug_ctrl;
+	uint32_t reserved2[2];
+	uint32_t fifo_stat;
+	uint32_t fifo_thresh;
+	uint32_t reserved3[932];
+	uint32_t multi_dma;
+	uint32_t reserved4[2];
+	uint32_t rollback;
+};
+
+check_member(mt_i2c_regs, multi_dma, 0xf8c);
+
+void mtk_i2c_init(uint8_t bus);
+
+#endif /* SOC_MEDIATEK_MT8183_I2C_H */
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0a4d78b494819f45951f78e5a618021000cf3463
Gerrit-Change-Number: 30976
Gerrit-PatchSet: 1
Gerrit-Owner: wang qii Qii.Wang@mediatek.com
Gerrit-MessageType: newchange



    

Change in ...coreboot[master]: mediatek/mt8183: Add I2C driver code