[XS] Change in coreboot[master]: mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7

[Dtrain Hsu (Code Review)]

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75644?usp=email )

Change subject: mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7
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mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7

Uldren does not have PCIE device and should disable PCIE RP7 and
GPP_D7 for preventing PCIe controller not power gate.

BUG=b:283735051
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: Ia8a2c0f5530c7a056e8d706c651cac1d49b2091c
Signed-off-by: Dtrain Hsu 
---
M src/mainboard/google/brya/variants/uldren/gpio.c
M src/mainboard/google/brya/variants/uldren/overridetree.cb
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/75644/1

diff --git a/src/mainboard/google/brya/variants/uldren/gpio.c b/src/mainboard/google/brya/variants/uldren/gpio.c
index e1e5e8c..c0c43814 100644
--- a/src/mainboard/google/brya/variants/uldren/gpio.c
+++ b/src/mainboard/google/brya/variants/uldren/gpio.c
@@ -21,6 +21,8 @@
    PAD_CFG_GPO(GPP_C1, 1, DEEP),
    /* D6  : SRCCLKREQ1# ==> WWAN_EN */
    PAD_CFG_GPO(GPP_D6, 1, DEEP),
+	/* D7  : SRCCLKREQ2# ==> NC */
+	PAD_NC(GPP_D7, NONE),
    /* D8  : SRCCLKREQ3# ==> NC */
    PAD_NC(GPP_D8, NONE),
    /* D15 : ISH_UART0_RTS# ==> NC */
diff --git a/src/mainboard/google/brya/variants/uldren/overridetree.cb b/src/mainboard/google/brya/variants/uldren/overridetree.cb
index 77b86552..a873a62 100644
--- a/src/mainboard/google/brya/variants/uldren/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldren/overridetree.cb
@@ -353,6 +353,7 @@
    			end
    		end
    	end
+		device ref pcie_rp7 off end
    	device ref hda on
    		chip drivers/generic/max98357a
    			register "hid" = ""MX98360A""