[S] Change in coreboot[master]: sb,soc/amd,intel: Sync FADT entries visually

[Shelley Chen (Code Review)]

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74912 )

Change subject: sb,soc/amd,intel: Sync FADT entries visually
......................................................................

sb,soc/amd,intel: Sync FADT entries visually

Change-Id: I20a66dce1612ab4394c26f9b0943dac14bcdcfc4
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74912
Tested-by: build bot (Jenkins) 
Reviewed-by: Elyes Haouas 
---
M src/soc/intel/apollolake/acpi.c
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/quark/acpi.c
M src/soc/intel/xeon_sp/skx/soc_acpi.c
M src/southbridge/amd/pi/hudson/fadt.c
6 files changed, 26 insertions(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Elyes Haouas: Looks good to me, approved

diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index b71ca64..68153f0 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -107,6 +107,8 @@

fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
    fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
    fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
    fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;

diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index db31e9e..2c27b15 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -115,11 +115,15 @@

fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
    fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
    fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
    fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;

fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
    fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
    fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
    fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;

@@ -134,7 +138,7 @@
    fadt->x_gpe0_blk.bit_offset = 0;
    fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
    fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
-	fadt->x_gpe0_blk.addrh = 0;
+	fadt->x_gpe0_blk.addrh = 0x0;
 }

unsigned long southbridge_write_acpi_tables(const struct device *device,
diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c
index af99af1..6ddcc08 100644
--- a/src/soc/intel/denverton_ns/acpi.c
+++ b/src/soc/intel/denverton_ns/acpi.c
@@ -103,7 +103,7 @@
    fadt->x_pm2_cnt_blk.bit_offset = 0;
    fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
    fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
-	fadt->x_pm2_cnt_blk.addrh = 0x00;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;

/* PM1 Timer Register */
    fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
@@ -111,7 +111,7 @@
    fadt->x_pm_tmr_blk.bit_offset = 0;
    fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
    fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
-	fadt->x_pm_tmr_blk.addrh = 0x00;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
 }

static acpi_tstate_t denverton_tss_table[] = {
diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c
index 68e1989..8e36723 100644
--- a/src/soc/intel/quark/acpi.c
+++ b/src/soc/intel/quark/acpi.c
@@ -58,7 +58,7 @@
    fadt->x_gpe0_blk.bit_offset = 0;
    fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
    fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
-	fadt->x_gpe0_blk.addrh = 0;
+	fadt->x_gpe0_blk.addrh = 0x0;

/* Display the base registers */
    printk(BIOS_SPEW, "FADT:\n");
diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c
index fc00dcb..33e7c1a 100644
--- a/src/soc/intel/xeon_sp/skx/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c
@@ -55,7 +55,7 @@
    fadt->x_pm2_cnt_blk.bit_offset = 0;
    fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
    fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
-	fadt->x_pm2_cnt_blk.addrh = 0x00;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;

/* PM1 Timer Register */
    fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
@@ -63,7 +63,7 @@
    fadt->x_pm_tmr_blk.bit_offset = 0;
    fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
    fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
-	fadt->x_pm_tmr_blk.addrh = 0x00;
+	fadt->x_pm_tmr_blk.addrh = 0x0;

}

diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c
index f85b2d5..701ceed 100644
--- a/src/southbridge/amd/pi/hudson/fadt.c
+++ b/src/southbridge/amd/pi/hudson/fadt.c
@@ -75,7 +75,7 @@
    fadt->x_pm_tmr_blk.addrh = 0x0;

fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; /* EventStatus + Event Enable */
+	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
    fadt->x_gpe0_blk.bit_offset = 0;
    fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
    fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;