Attention is currently required from: Martin Roth, Tim Wawrzynczak, Sugnan Prabhu S, Subrata Banik, Angel Pons, Balaji Manigandan, Aamir Bohra. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49479 )
Change subject: mb/intel/shadowmountain: Add bootblock and verstage code ......................................................................
Patch Set 4:
(7 comments)
File src/mainboard/intel/shadowmountain/bootblock.c:
https://review.coreboot.org/c/coreboot/+/49479/comment/02d6b74d_44c448d6 PS3, Line 9: const struct pad_config *pads; : size_t num; : : pads = variant_early_gpio_table(&num); : gpio_configure_pads(pads, num);
variant_configure_early_gpios();
Done
File src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/49479/comment/c9b79478_19e37559 PS3, Line 2: ##
drop this `##`
Done
File src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49479/comment/c87a31bc_72319c35 PS3, Line 7: # GPE configuration : # Note that GPE events called out in ASL code rely on this : # route. i.e. If this route changes then the affected GPE : # offset bits also need to be changed. : register "pmc_gpe0_dw0" = "GPP_C" : register "pmc_gpe0_dw1" = "GPP_D" : register "pmc_gpe0_dw2" = "GPP_E"
Is this correct?
Yes.
https://review.coreboot.org/c/coreboot/+/49479/comment/648121c0_a15fec7c PS3, Line 15: # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f : register "gen1_dec" = "0x00fc0801" : register "gen2_dec" = "0x000c0201" : # EC memory map range is 0x900-0x9ff : register "gen3_dec" = "0x00fc0901"
Is this still valid?
yes.
File src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/49479/comment/b987fb71_df6bc41f PS3, Line 8: early_gpio_table
in ADLRVP we had early_gpio.c and gpio.c. […]
Done
https://review.coreboot.org/c/coreboot/+/49479/comment/677c6dde_793259cb PS3, Line 41: constrains
constrain*t*s
Done
https://review.coreboot.org/c/coreboot/+/49479/comment/e572d99d_7556c094 PS3, Line 52: const struct pad_config *__weak variant_early_gpio_table(size_t *num) : { : *num = ARRAY_SIZE(early_gpio_table); : return early_gpio_table; : }
void variant_configure_early_gpios(void) […]
Done
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V Sowmya (Code Review)