Change in coreboot[master]: src/: Remove g_ prefixes and _g suffixes from variables - coreboot-gerrit

29 Nov 2019

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37358 )
Change subject: src/: Remove g_ prefixes and _g suffixes from variables
......................................................................
src/: Remove g_ prefixes and _g suffixes from variables
These were often used to distinguish CAR_GLOBAL variables that weren't
directly usable. Since we're getting rid of this special case, also get
rid of the marker.
This change was created using coccinelle and the following script:
    @match@
    type T;
    identifier old =~ "^(g_.*|.*_g)$";
    @@
    old
@script:python global_marker@
    old << match.old;
    new;
    @@
    new = old
    if old[0:2] == "g_":
      new = new[2:]
if new[-2:] == "_g":
      new = new[:-2]
coccinelle.new = new
@@
    identifier match.old, global_marker.new;
    @@
    - old
    + new
@@
    type T;
    identifier match.old, global_marker.new;
    @@
    - T old;
    + T new;
@@
    type T;
    identifier match.old, global_marker.new;
    @@
    - T old
    + T new
     = ...;
Change-Id: I4936ff9780a0d3ed9b8b539772bc48887f8d5eed
Signed-off-by: Patrick Georgi pgeorgi@google.com
---
M src/cpu/intel/common/fsb.c
M src/cpu/intel/turbo/turbo.c
M src/cpu/x86/lapic/apic_timer.c
M src/cpu/x86/tsc/delay_tsc.c
M src/drivers/aspeed/common/ast_post.c
M src/drivers/elog/elog.c
M src/drivers/i2c/tpm/cr50.c
M src/drivers/i2c/tpm/tis.c
M src/drivers/i2c/tpm/tpm.c
M src/drivers/pc80/pc/i8254.c
M src/drivers/spi/flashconsole.c
M src/drivers/spi/tpm/tpm.c
M src/drivers/vpd/vpd.c
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/nvidia/tegra/i2c.c
M src/southbridge/intel/common/spi.c
M src/vendorcode/google/chromeos/ramoops.c
18 files changed, 312 insertions(+), 309 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/37358/1

diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c
index 0004ead..7b3f3c3 100644
--- a/src/cpu/intel/common/fsb.c
+++ b/src/cpu/intel/common/fsb.c
@@ -20,8 +20,8 @@
 #include <commonlib/helpers.h>
 #include <delay.h>
-static u32 g_timer_fsb CAR_GLOBAL;
-static u32 g_timer_tsc CAR_GLOBAL;
+static u32 timer_fsb;
+static u32 timer_tsc;
/* This is not an architectural MSR. */
 #define MSR_PLATFORM_INFO 0xce
@@ -99,8 +99,8 @@
    ret = get_fsb_tsc(&fsb, &ratio);
    if (ret == 0) {
    	u32 tsc = 100 * DIV_ROUND_CLOSEST(ratio * fsb, 100);
-		car_set_var(g_timer_fsb, fsb);
-		car_set_var(g_timer_tsc, tsc);
+		car_set_var(timer_fsb, fsb);
+		car_set_var(timer_tsc, tsc);
    	return;
    }
@@ -110,8 +110,8 @@
    	printk(BIOS_ERR, "CPU not supported\n");
/* Set some semi-ridiculous defaults. */
-	car_set_var(g_timer_fsb, 500);
-	car_set_var(g_timer_tsc, 5000);
+	car_set_var(timer_fsb, 500);
+	car_set_var(timer_tsc, 5000);
    return;
 }
@@ -119,24 +119,24 @@
 {
    u32 fsb;
-	fsb = car_get_var(g_timer_fsb);
+	fsb = car_get_var(timer_fsb);
    if (fsb > 0)
    	return fsb;
resolve_timebase();
-	return car_get_var(g_timer_fsb);
+	return car_get_var(timer_fsb);
 }
unsigned long tsc_freq_mhz(void)
 {
    u32 tsc;
-	tsc = car_get_var(g_timer_tsc);
+	tsc = car_get_var(timer_tsc);
    if (tsc > 0)
    	return tsc;
resolve_timebase();
-	return car_get_var(g_timer_tsc);
+	return car_get_var(timer_tsc);
 }
/**
diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c
index d0b4941..b61e768 100644
--- a/src/cpu/intel/turbo/turbo.c
+++ b/src/cpu/intel/turbo/turbo.c
@@ -27,16 +27,16 @@
 {
 }
 #else
-static int g_turbo_state = TURBO_UNKNOWN;
+static int turbo_state = TURBO_UNKNOWN;
static inline int get_global_turbo_state(void)
 {
-	return g_turbo_state;
+	return turbo_state;
 }
static inline void set_global_turbo_state(int state)
 {
-	g_turbo_state = state;
+	turbo_state = state;
 }
 #endif
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index 8f0f7af..0b3f691 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -62,7 +62,7 @@
    int initialized;
    struct mono_time time;
    uint32_t last_value;
-} mono_counter_g;
+} mono_counter;
void timer_monotonic_get(struct mono_time *mt)
 {
@@ -70,7 +70,7 @@
    uint32_t usecs_elapsed;
    uint32_t timer_fsb;
-	if (!mono_counter_g.initialized) {
+	if (!mono_counter.initialized) {
    	init_timer();
    	timer_fsb = get_timer_fsb();
    	/* An FSB frequency of 200Mhz provides a 20 second polling
@@ -80,22 +80,22 @@
    		printk(BIOS_WARNING,
    		       "apic timer freq (%d) may be too fast.\n",
    		       timer_fsb);
-		mono_counter_g.last_value = lapic_read(LAPIC_TMCCT);
-		mono_counter_g.initialized = 1;
+		mono_counter.last_value = lapic_read(LAPIC_TMCCT);
+		mono_counter.initialized = 1;
    }
timer_fsb = get_timer_fsb();
    current_tick = lapic_read(LAPIC_TMCCT);
    /* Note that the APIC timer counts down. */
-	usecs_elapsed = (mono_counter_g.last_value - current_tick) / timer_fsb;
+	usecs_elapsed = (mono_counter.last_value - current_tick) / timer_fsb;
/* Update current time and tick values only if a full tick occurred. */
    if (usecs_elapsed) {
-		mono_time_add_usecs(&mono_counter_g.time, usecs_elapsed);
-		mono_counter_g.last_value = current_tick;
+		mono_time_add_usecs(&mono_counter.time, usecs_elapsed);
+		mono_counter.last_value = current_tick;
    }
/* Save result. */
-	*mt = mono_counter_g.time;
+	*mt = mono_counter.time;
 }
 #endif
diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c
index fe6ae5b..1a57e77 100644
--- a/src/cpu/x86/tsc/delay_tsc.c
+++ b/src/cpu/x86/tsc/delay_tsc.c
@@ -48,11 +48,11 @@
    int initialized;
    struct mono_time time;
    uint64_t last_value;
-} mono_counter_g;
+} mono_counter;
static inline struct monotonic_counter *get_monotonic_context(void)
 {
-	return &mono_counter_g;
+	return &mono_counter;
 }
void timer_monotonic_get(struct mono_time *mt)
diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c
index d14082e..f692b1b 100644
--- a/src/drivers/aspeed/common/ast_post.c
+++ b/src/drivers/aspeed/common/ast_post.c
@@ -793,14 +793,14 @@
    		dqidly++;
    }
    /* Search margin */
-	g_dqidly = g_dqsip = g_margin = g_side = 0;
+	dqidly = dqsip = margin = side = 0;
for (dqidly = 0; dqidly < 32; dqidly++) {
    	for (dqsip = 0; dqsip < 2; dqsip++) {
    		if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
    			continue;
    		diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
-			if ((diff+2) < g_margin)
+			if ((diff+2) < margin)
    			continue;
    		passcnt[0] = passcnt[1] = 0;
    		for (dlli = pass[dqidly][dqsip][0]; dlli > 0  && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
@@ -808,23 +808,23 @@
    		if (passcnt[0] > passcnt[1])
    			passcnt[0] = passcnt[1];
    		passcnt[1] = 0;
-			if (passcnt[0] > g_side)
-				passcnt[1] = passcnt[0] - g_side;
-			if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
-				g_margin = diff;
-				g_dqidly = dqidly;
-				g_dqsip  = dqsip;
-				g_side   = passcnt[0];
-			} else if (passcnt[1] > 1 && g_side < 8) {
-				if (diff > g_margin)
-					g_margin = diff;
-				g_dqidly = dqidly;
-				g_dqsip  = dqsip;
-				g_side   = passcnt[0];
+			if (passcnt[0] > side)
+				passcnt[1] = passcnt[0] - side;
+			if (diff > (margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
+				margin = diff;
+				dqidly = dqidly;
+				dqsip  = dqsip;
+				side   = passcnt[0];
+			} else if (passcnt[1] > 1 && side < 8) {
+				if (diff > margin)
+					margin = diff;
+				dqidly = dqidly;
+				dqsip  = dqsip;
+				side   = passcnt[0];
    		}
    	}
    }
-	reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
+	reg_mcr18 = reg_mcr18 | (dqidly << 16) | (dqsip << 23);
    ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
}
diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c
index 768ea28..97a9c7f 100644
--- a/src/drivers/elog/elog.c
+++ b/src/drivers/elog/elog.c
@@ -65,14 +65,14 @@
    enum elog_init_state elog_initialized;
 };
-static struct elog_state g_elog_state;
+static struct elog_state elog_state;
#define ELOG_SIZE (4 * KiB)
 static uint8_t elog_mirror_buf[ELOG_SIZE];
static inline struct region_device *mirror_dev_get(void)
 {
-	return &g_elog_state.mirror_dev.rdev;
+	return &elog_state.mirror_dev.rdev;
 }
static size_t elog_events_start(void)
@@ -83,7 +83,7 @@
static size_t elog_events_total_space(void)
 {
-	return region_device_sz(&g_elog_state.nv_dev) - elog_events_start();
+	return region_device_sz(&elog_state.nv_dev) - elog_events_start();
 }
static struct event_header *elog_get_event_buffer(size_t offset, size_t size)
@@ -93,8 +93,9 @@
static struct event_header *elog_get_next_event_buffer(size_t size)
 {
-	elog_debug("ELOG: new event at offset 0x%zx\n", g_elog_state.mirror_last_write);
-	return elog_get_event_buffer(g_elog_state.mirror_last_write, size);
+	elog_debug("ELOG: new event at offset 0x%zx\n",
+		   elog_state.mirror_last_write);
+	return elog_get_event_buffer(elog_state.mirror_last_write, size);
 }
static void elog_put_event_buffer(struct event_header *event)
@@ -105,53 +106,53 @@
 static size_t elog_mirror_reset_last_write(void)
 {
    /* Return previous write value. */
-	size_t prev = g_elog_state.mirror_last_write;
+	size_t prev = elog_state.mirror_last_write;
-	g_elog_state.mirror_last_write = 0;
+	elog_state.mirror_last_write = 0;
    return prev;
 }
static void elog_mirror_increment_last_write(size_t size)
 {
-	g_elog_state.mirror_last_write += size;
+	elog_state.mirror_last_write += size;
 }
static void elog_nv_reset_last_write(void)
 {
-	g_elog_state.nv_last_write = 0;
+	elog_state.nv_last_write = 0;
 }
static void elog_nv_increment_last_write(size_t size)
 {
-	g_elog_state.nv_last_write += size;
+	elog_state.nv_last_write += size;
 }
static void elog_nv_needs_possible_erase(void)
 {
    /* If last write is 0 it means it is already erased. */
-	if (g_elog_state.nv_last_write != 0)
-		g_elog_state.nv_last_write = NV_NEEDS_ERASE;
+	if (elog_state.nv_last_write != 0)
+		elog_state.nv_last_write = NV_NEEDS_ERASE;
 }
static bool elog_should_shrink(void)
 {
-	return g_elog_state.mirror_last_write >= g_elog_state.full_threshold;
+	return elog_state.mirror_last_write >= elog_state.full_threshold;
 }
static bool elog_nv_needs_erase(void)
 {
-	return g_elog_state.nv_last_write == NV_NEEDS_ERASE;
+	return elog_state.nv_last_write == NV_NEEDS_ERASE;
 }
static bool elog_nv_needs_update(void)
 {
-	return g_elog_state.nv_last_write != g_elog_state.mirror_last_write;
+	return elog_state.nv_last_write != elog_state.mirror_last_write;
 }
static size_t elog_nv_region_to_update(size_t *offset)
 {
-	*offset = g_elog_state.nv_last_write;
-	return g_elog_state.mirror_last_write - g_elog_state.nv_last_write;
+	*offset = elog_state.nv_last_write;
+	return elog_state.mirror_last_write - elog_state.nv_last_write;
 }
/*
@@ -335,7 +336,7 @@
    	return;
/* Write the data to flash */
-	if (rdev_writeat(&g_elog_state.nv_dev, address, offset, size) != size)
+	if (rdev_writeat(&elog_state.nv_dev, address, offset, size) != size)
    	printk(BIOS_ERR, "ELOG: NV Write failed at 0x%zx, size 0x%zx\n",
    		offset, size);
@@ -348,11 +349,11 @@
  */
 static void elog_nv_erase(void)
 {
-	size_t size = region_device_sz(&g_elog_state.nv_dev);
+	size_t size = region_device_sz(&elog_state.nv_dev);
    elog_debug("%s()\n", __func__);
/* Erase the sectors in this region */
-	if (rdev_eraseat(&g_elog_state.nv_dev, 0, size) != size)
+	if (rdev_eraseat(&elog_state.nv_dev, 0, size) != size)
    	printk(BIOS_ERR, "ELOG: erase failure.\n");
 }
@@ -411,11 +412,11 @@
    void *mirror_buffer;
    const struct region_device *rdev = mirror_dev_get();
-	size_t size = region_device_sz(&g_elog_state.nv_dev);
+	size_t size = region_device_sz(&elog_state.nv_dev);
/* Fill memory buffer by reading from SPI */
    mirror_buffer = rdev_mmap_full(rdev);
-	if (rdev_readat(&g_elog_state.nv_dev, mirror_buffer, 0, size) != size) {
+	if (rdev_readat(&elog_state.nv_dev, mirror_buffer, 0, size) != size) {
    	rdev_munmap(rdev, mirror_buffer);
    	printk(BIOS_ERR, "ELOG: NV read failure.\n");
    	return -1;
@@ -580,7 +581,7 @@
 static int elog_shrink(void)
 {
    if (elog_should_shrink())
-		return elog_shrink_by_size(g_elog_state.shrink_size);
+		return elog_shrink_by_size(elog_state.shrink_size);
    return 0;
 }
@@ -593,12 +594,13 @@
    if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED))
    	return NULL;
-	if (!region_device_sz(&g_elog_state.nv_dev))
+	if (!region_device_sz(&elog_state.nv_dev))
    	return NULL;
/* Get a view into the read-only boot device. */
-	return rdev_mmap(boot_device_ro(), region_device_offset(&g_elog_state.nv_dev),
-			region_device_sz(&g_elog_state.nv_dev));
+	return rdev_mmap(boot_device_ro(),
+			 region_device_offset(&elog_state.nv_dev),
+			 region_device_sz(&elog_state.nv_dev));
 }
/*
@@ -611,7 +613,7 @@
    int len = sizeof(struct smbios_type15);
    uintptr_t log_address;
-	size_t elog_size = region_device_sz(&g_elog_state.nv_dev);
+	size_t elog_size = region_device_sz(&elog_state.nv_dev);
if (CONFIG(ELOG_CBMEM)) {
    	/* Save event log buffer into CBMEM for the OS to read */
@@ -665,7 +667,7 @@
 {
    size_t total_size;
    size_t reserved_space = ELOG_MIN_AVAILABLE_ENTRIES * MAX_EVENT_SIZE;
-	struct region_device *rdev = &g_elog_state.nv_dev;
+	struct region_device *rdev = &elog_state.nv_dev;
elog_debug("%s()\n", __func__);
@@ -688,10 +690,10 @@
    total_size = MIN(ELOG_SIZE, region_device_sz(rdev));
    rdev_chain(rdev, rdev, 0, total_size);
-	g_elog_state.full_threshold = total_size - reserved_space;
-	g_elog_state.shrink_size = total_size * ELOG_SHRINK_PERCENTAGE / 100;
+	elog_state.full_threshold = total_size - reserved_space;
+	elog_state.shrink_size = total_size * ELOG_SHRINK_PERCENTAGE / 100;
-	if (reserved_space > g_elog_state.shrink_size) {
+	if (reserved_space > elog_state.shrink_size) {
    	printk(BIOS_ERR, "ELOG: SHRINK_PERCENTAGE too small\n");
    	return -1;
    }
@@ -734,7 +736,7 @@
    if (elog_scan_flash() < 0) {
    	printk(BIOS_ERR, "ELOG: Sync back from NV storage failed.\n");
    	elog_debug_dump_buffer("ELOG: Buffer from NV:\n");
-		g_elog_state.elog_initialized = ELOG_BROKEN;
+		elog_state.elog_initialized = ELOG_BROKEN;
    	return -1;
    }
@@ -776,7 +778,7 @@
 {
    void *mirror_buffer;
    size_t elog_size;
-	switch (g_elog_state.elog_initialized) {
+	switch (elog_state.elog_initialized) {
    case ELOG_UNINITIALIZED:
    	break;
    case ELOG_INITIALIZED:
@@ -784,7 +786,7 @@
    case ELOG_BROKEN:
    	return -1;
    }
-	g_elog_state.elog_initialized = ELOG_BROKEN;
+	elog_state.elog_initialized = ELOG_BROKEN;
elog_debug("elog_init()\n");
@@ -792,19 +794,20 @@
    if (elog_find_flash() < 0)
    	return -1;
-	elog_size = region_device_sz(&g_elog_state.nv_dev);
+	elog_size = region_device_sz(&elog_state.nv_dev);
    mirror_buffer = elog_mirror_buf;
    if (!mirror_buffer) {
    	printk(BIOS_ERR, "ELOG: Unable to allocate backing store\n");
    	return -1;
    }
-	mem_region_device_rw_init(&g_elog_state.mirror_dev, mirror_buffer, elog_size);
+	mem_region_device_rw_init(&elog_state.mirror_dev, mirror_buffer,
+				  elog_size);
/*
     * Mark as initialized to allow elog_init() to be called and deemed
     * successful in the prepare/shrink path which adds events.
     */
-	g_elog_state.elog_initialized = ELOG_INITIALIZED;
+	elog_state.elog_initialized = ELOG_INITIALIZED;
/* Load the log from flash and prepare the flash if necessary. */
    if (elog_scan_flash() < 0 && elog_prepare_empty() < 0) {
@@ -813,8 +816,8 @@
    }
printk(BIOS_INFO, "ELOG: area is %zu bytes, full threshold %d,"
-	       " shrink size %d\n", region_device_sz(&g_elog_state.nv_dev),
-		g_elog_state.full_threshold, g_elog_state.shrink_size);
+	       " shrink size %d\n", region_device_sz(&elog_state.nv_dev),
+	       elog_state.full_threshold, elog_state.shrink_size);
if (ENV_PAYLOAD_LOADER)
    	elog_add_boot_count();
diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c
index f386dac..8ea544d 100644
--- a/src/drivers/i2c/tpm/cr50.c
+++ b/src/drivers/i2c/tpm/cr50.c
@@ -54,7 +54,7 @@
    uint8_t buf[CR50_MAX_BUFSIZE + sizeof(uint8_t)];
 };
-static struct tpm_inf_dev g_tpm_dev;
+static struct tpm_inf_dev tpm_dev;
__weak int tis_plat_irq_status(void)
 {
@@ -101,14 +101,14 @@
 static int cr50_i2c_read(struct tpm_chip *chip, uint8_t addr,
    		 uint8_t *buffer, size_t len)
 {
-	if (g_tpm_dev.addr == 0)
+	if (tpm_dev.addr == 0)
    	return -1;
/* Clear interrupt before starting transaction */
    tis_plat_irq_status();
/* Send the register address byte to the TPM */
-	if (i2c_write_raw(g_tpm_dev.bus, g_tpm_dev.addr, &addr, 1)) {
+	if (i2c_write_raw(tpm_dev.bus, tpm_dev.addr, &addr, 1)) {
    	printk(BIOS_ERR, "%s: Address write failed\n", __func__);
    	return -1;
    }
@@ -118,7 +118,7 @@
    	return -1;
/* Read response data from the TPM */
-	if (i2c_read_raw(g_tpm_dev.bus, g_tpm_dev.addr, buffer, len)) {
+	if (i2c_read_raw(tpm_dev.bus, tpm_dev.addr, buffer, len)) {
    	printk(BIOS_ERR, "%s: Read response failed\n", __func__);
    	return -1;
    }
@@ -143,20 +143,20 @@
 static int cr50_i2c_write(struct tpm_chip *chip,
    		  uint8_t addr, uint8_t *buffer, size_t len)
 {
-	if (g_tpm_dev.addr == 0)
+	if (tpm_dev.addr == 0)
    	return -1;
    if (len > CR50_MAX_BUFSIZE)
    	return -1;
/* Prepend the 'register address' to the buffer */
-	g_tpm_dev.buf[0] = addr;
-	memcpy(g_tpm_dev.buf + 1, buffer, len);
+	tpm_dev.buf[0] = addr;
+	memcpy(tpm_dev.buf + 1, buffer, len);
/* Clear interrupt before starting transaction */
    tis_plat_irq_status();
/* Send write request buffer with address */
-	if (i2c_write_raw(g_tpm_dev.bus, g_tpm_dev.addr, g_tpm_dev.buf, len + 1)) {
+	if (i2c_write_raw(tpm_dev.bus, tpm_dev.addr, tpm_dev.buf, len + 1)) {
    	printk(BIOS_ERR, "%s: Error writing to TPM\n", __func__);
    	return -1;
    }
@@ -494,8 +494,8 @@
    	return -1;
    }
-	g_tpm_dev.bus = bus;
-	g_tpm_dev.addr = dev_addr;
+	tpm_dev.bus = bus;
+	tpm_dev.addr = dev_addr;
cr50_vendor_init(chip);
diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c
index d791a56..3ce1df5 100644
--- a/src/drivers/i2c/tpm/tis.c
+++ b/src/drivers/i2c/tpm/tis.c
@@ -26,7 +26,7 @@
 #include "tpm.h"
/* global structure for tpm chip data */
-static struct tpm_chip g_chip;
+static struct tpm_chip chip;
#define TPM_CMD_COUNT_BYTE 2
 #define TPM_CMD_ORDINAL_BYTE 6
@@ -35,15 +35,15 @@
 {
    int rc;
-	if (g_chip.is_open) {
+	if (chip.is_open) {
    	printk(BIOS_DEBUG, "tis_open() called twice.\n");
    	return -1;
    }
-	rc = tpm_vendor_init(&g_chip, CONFIG_DRIVER_TPM_I2C_BUS,
+	rc = tpm_vendor_init(&chip, CONFIG_DRIVER_TPM_I2C_BUS,
    		     CONFIG_DRIVER_TPM_I2C_ADDR);
    if (rc < 0)
-		g_chip.is_open = 0;
+		chip.is_open = 0;
if (rc)
    	return -1;
@@ -53,9 +53,9 @@
int tis_close(void)
 {
-	if (g_chip.is_open) {
-		tpm_vendor_cleanup(&g_chip);
-		g_chip.is_open = 0;
+	if (chip.is_open) {
+		tpm_vendor_cleanup(&chip);
+		chip.is_open = 0;
    }
return 0;
@@ -76,7 +76,7 @@
    memcpy(&count, sbuf + TPM_CMD_COUNT_BYTE, sizeof(count));
    count = be32_to_cpu(count);
-	if (!g_chip.vendor.send || !g_chip.vendor.status || !g_chip.vendor.cancel)
+	if (!chip.vendor.send || !chip.vendor.status || !chip.vendor.cancel)
    	return -1;
if (count == 0) {
@@ -90,7 +90,7 @@
    }
ASSERT(g_chip.vendor.send);
-	rc = g_chip.vendor.send(&g_chip, (uint8_t *) sbuf, count);
+	rc = chip.vendor.send(&chip, (uint8_t *) sbuf, count);
    if (rc < 0) {
    	printk(BIOS_DEBUG, "tpm_transmit: tpm_send error\n");
    	goto out;
@@ -99,13 +99,13 @@
    int timeout = 2 * 60 * 1000; /* two minutes timeout */
    while (timeout) {
    	ASSERT(g_chip.vendor.status);
-		uint8_t status = g_chip.vendor.status(&g_chip);
-		if ((status & g_chip.vendor.req_complete_mask) ==
-		    g_chip.vendor.req_complete_val) {
+		uint8_t status = chip.vendor.status(&chip);
+		if ((status & chip.vendor.req_complete_mask) ==
+		    chip.vendor.req_complete_val) {
    		goto out_recv;
    	}
-		if (status == g_chip.vendor.req_canceled) {
+		if (status == chip.vendor.req_canceled) {
    		printk(BIOS_DEBUG,
    			"tpm_transmit: Operation Canceled\n");
    		rc = -1;
@@ -116,14 +116,14 @@
    }
ASSERT(g_chip.vendor.cancel);
-	g_chip.vendor.cancel(&g_chip);
+	chip.vendor.cancel(&chip);
    printk(BIOS_DEBUG, "tpm_transmit: Operation Timed out\n");
    rc = -1; //ETIME;
    goto out;
out_recv:
-	rc = g_chip.vendor.recv(&g_chip, (uint8_t *) rbuf, rbufsiz);
+	rc = chip.vendor.recv(&chip, (uint8_t *) rbuf, rbufsiz);
    if (rc < 0)
    	printk(BIOS_DEBUG, "tpm_transmit: tpm_recv: error %d\n", rc);
 out:
diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c
index 71641d0..009227e 100644
--- a/src/drivers/i2c/tpm/tpm.c
+++ b/src/drivers/i2c/tpm/tpm.c
@@ -80,7 +80,7 @@
    enum i2c_chip_type chip_type;
 };
-static struct tpm_inf_dev g_tpm_dev;
+static struct tpm_inf_dev tpm_dev;
/*
  * iic_tpm_read() - read from TPM register
@@ -101,20 +101,20 @@
    int rc;
    int count;
-	if (g_tpm_dev.addr == 0)
+	if (tpm_dev.addr == 0)
    	return -1;
-	switch (g_tpm_dev.chip_type) {
+	switch (tpm_dev.chip_type) {
    case SLB9635:
    case UNKNOWN:
    	/* slb9635 protocol should work in both cases */
    	for (count = 0; count < MAX_COUNT; count++) {
-			rc = i2c_write_raw(g_tpm_dev.bus, g_tpm_dev.addr,
+			rc = i2c_write_raw(tpm_dev.bus, tpm_dev.addr,
    				   &addr, 1);
    		if (rc == 0)
    			break;  /* success, break to skip sleep */
-			udelay(g_tpm_dev.sleep_short);
+			udelay(tpm_dev.sleep_short);
    	}
if (rc)
@@ -125,8 +125,8 @@
    	 * retrieving the data
    	 */
    	for (count = 0; count < MAX_COUNT; count++) {
-			udelay(g_tpm_dev.sleep_short);
-			rc = i2c_read_raw(g_tpm_dev.bus, g_tpm_dev.addr,
+			udelay(tpm_dev.sleep_short);
+			rc = i2c_read_raw(tpm_dev.bus, tpm_dev.addr,
    				  buffer, len);
    		if (rc == 0)
    			break;  /* success, break to skip sleep */
@@ -142,23 +142,23 @@
    	 * retries should usually not be needed, but are kept just to
    	 * be safe on the safe side.
    	 */
-		struct i2c_msg aseg = { .flags = 0, .slave = g_tpm_dev.addr,
+		struct i2c_msg aseg = { .flags = 0, .slave = tpm_dev.addr,
    				.buf = &addr, .len = 1 };
    	struct i2c_msg dseg = { .flags = I2C_M_RD,
-					.slave = g_tpm_dev.addr,
+					.slave = tpm_dev.addr,
    				.buf = buffer, .len = len };
    	for (count = 0; count < MAX_COUNT; count++) {
-			rc = i2c_transfer(g_tpm_dev.bus, &aseg, 1) ||
-			     i2c_transfer(g_tpm_dev.bus, &dseg, 1);
+			rc = i2c_transfer(tpm_dev.bus, &aseg, 1) ||
+			     i2c_transfer(tpm_dev.bus, &dseg, 1);
    		if (rc == 0)
    			break;  /* break here to skip sleep */
-			udelay(g_tpm_dev.sleep_short);
+			udelay(tpm_dev.sleep_short);
    	}
    }
    }
/* take care of 'guard time' */
-	udelay(g_tpm_dev.sleep_short);
+	udelay(tpm_dev.sleep_short);
    if (rc)
    	return -1;
@@ -179,14 +179,14 @@
    }
/* prepare send buffer */
-	g_tpm_dev.buf[0] = addr;
-	memcpy(&(g_tpm_dev.buf[1]), buffer, len);
+	tpm_dev.buf[0] = addr;
+	memcpy(&(tpm_dev.buf[1]), buffer, len);
-	if (g_tpm_dev.addr == 0)
+	if (tpm_dev.addr == 0)
    	return -1;
    for (count = 0; count < max_count; count++) {
-		rc = i2c_write_raw(g_tpm_dev.bus, g_tpm_dev.addr,
-				   g_tpm_dev.buf, len + 1);
+		rc = i2c_write_raw(tpm_dev.bus, tpm_dev.addr,
+				   tpm_dev.buf, len + 1);
    	if (rc == 0)
    		break;  /* success, break to skip sleep */
@@ -194,7 +194,7 @@
    }
/* take care of 'guard time' */
-	udelay(g_tpm_dev.sleep_short);
+	udelay(tpm_dev.sleep_short);
    if (rc)
    	return -1;
@@ -219,8 +219,8 @@
  */
 static int iic_tpm_write(uint8_t addr, uint8_t *buffer, size_t len)
 {
-	return iic_tpm_write_generic(addr, buffer, len, g_tpm_dev.sleep_short,
-			MAX_COUNT);
+	return iic_tpm_write_generic(addr, buffer, len, tpm_dev.sleep_short,
+				     MAX_COUNT);
 }
/*
@@ -229,8 +229,8 @@
  * */
 static int iic_tpm_write_long(uint8_t addr, uint8_t *buffer, size_t len)
 {
-	return iic_tpm_write_generic(addr, buffer, len, g_tpm_dev.sleep_long,
-			MAX_COUNT_LONG);
+	return iic_tpm_write_generic(addr, buffer, len, tpm_dev.sleep_long,
+				     MAX_COUNT_LONG);
 }
static int check_locality(struct tpm_chip *chip, int loc)
@@ -479,11 +479,11 @@
    int ret;
    long sw_run_duration = SLEEP_DURATION_PROBE_MS;
-	g_tpm_dev.chip_type = UNKNOWN;
-	g_tpm_dev.bus = bus;
-	g_tpm_dev.addr = addr;
-	g_tpm_dev.sleep_short = SLEEP_DURATION;
-	g_tpm_dev.sleep_long = SLEEP_DURATION_LONG;
+	tpm_dev.chip_type = UNKNOWN;
+	tpm_dev.bus = bus;
+	tpm_dev.addr = addr;
+	tpm_dev.sleep_short = SLEEP_DURATION;
+	tpm_dev.sleep_long = SLEEP_DURATION_LONG;
/*
     * Probe TPM. Check if the TPM_ACCESS register's ValidSts bit is set(1)
@@ -522,11 +522,11 @@
    	return -1;
    }
-	g_tpm_dev.chip_type = UNKNOWN;
-	g_tpm_dev.bus = bus;
-	g_tpm_dev.addr = dev_addr;
-	g_tpm_dev.sleep_short = SLEEP_DURATION;
-	g_tpm_dev.sleep_long = SLEEP_DURATION_LONG;
+	tpm_dev.chip_type = UNKNOWN;
+	tpm_dev.bus = bus;
+	tpm_dev.addr = dev_addr;
+	tpm_dev.sleep_short = SLEEP_DURATION;
+	tpm_dev.sleep_long = SLEEP_DURATION_LONG;
memset(&chip->vendor, 0, sizeof(struct tpm_vendor_specific));
    chip->is_open = 1;
@@ -547,9 +547,9 @@
    	goto out_err;
if (vendor == TPM_TIS_I2C_DID_VID_9645) {
-		g_tpm_dev.chip_type = SLB9645;
+		tpm_dev.chip_type = SLB9645;
    } else if (be32_to_cpu(vendor) == TPM_TIS_I2C_DID_VID_9635) {
-		g_tpm_dev.chip_type = SLB9635;
+		tpm_dev.chip_type = SLB9635;
    } else {
    	printk(BIOS_DEBUG, "Vendor ID 0x%08x not recognized.\n",
    		vendor);
@@ -557,8 +557,8 @@
    }
printk(BIOS_DEBUG, "I2C TPM %u:%02x (chip type %s device-id 0x%X)\n",
-	       g_tpm_dev.bus, g_tpm_dev.addr,
-	       chip_name[g_tpm_dev.chip_type], vendor >> 16);
+	       tpm_dev.bus, tpm_dev.addr,
+	       chip_name[tpm_dev.chip_type], vendor >> 16);
/*
     * A timeout query to TPM can be placed here.
diff --git a/src/drivers/pc80/pc/i8254.c b/src/drivers/pc80/pc/i8254.c
index 9d23d46..0b04b393 100644
--- a/src/drivers/pc80/pc/i8254.c
+++ b/src/drivers/pc80/pc/i8254.c
@@ -106,19 +106,19 @@
 }
#if CONFIG(UNKNOWN_TSC_RATE)
-static u32 g_timer_tsc;
+static u32 timer_tsc;
unsigned long tsc_freq_mhz(void)
 {
-	if (g_timer_tsc > 0)
-		return g_timer_tsc;
+	if (timer_tsc > 0)
+		return timer_tsc;
-	g_timer_tsc = calibrate_tsc_with_pit();
+	timer_tsc = calibrate_tsc_with_pit();
/* Set some semi-ridiculous rate if approximation fails. */
-	if (g_timer_tsc == 0)
-		g_timer_tsc = 5000;
+	if (timer_tsc == 0)
+		timer_tsc = 5000;
-	return g_timer_tsc;
+	return timer_tsc;
 }
 #endif
diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c
index 8874812..cdf55e5 100644
--- a/src/drivers/spi/flashconsole.c
+++ b/src/drivers/spi/flashconsole.c
@@ -23,15 +23,15 @@
 #define LINE_BUFFER_SIZE 128
 #define READ_BUFFER_SIZE 0x100
-static const struct region_device *g_rdev_ptr CAR_GLOBAL;
+static const struct region_device *rdev_ptr;
 static struct region_device g_rdev CAR_GLOBAL;
 static uint8_t g_line_buffer[LINE_BUFFER_SIZE] CAR_GLOBAL;
-static size_t g_offset CAR_GLOBAL;
-static size_t g_line_offset CAR_GLOBAL;
+static size_t offset;
+static size_t line_offset;
void flashconsole_init(void)
 {
-	struct region_device *rdev = car_get_var_ptr(&g_rdev);
+	struct region_device *rdev = car_get_var_ptr(&rdev);
    uint8_t buffer[READ_BUFFER_SIZE];
    size_t size;
    size_t offset = 0;
@@ -77,14 +77,14 @@
    	return;
    }
-	car_set_var(g_offset, offset);
+	car_set_var(offset, offset);
    /* Set g_rdev_ptr last so tx_byte doesn't get executed early */
-	car_set_var(g_rdev_ptr, rdev);
+	car_set_var(rdev_ptr, rdev);
 }
void flashconsole_tx_byte(unsigned char c)
 {
-	const struct region_device *rdev = car_get_var(g_rdev_ptr);
+	const struct region_device *rdev = car_get_var(rdev_ptr);
    uint8_t *line_buffer;
    size_t offset;
    size_t len;
@@ -93,13 +93,13 @@
    if (!rdev)
    	return;
-	line_buffer = car_get_var_ptr(g_line_buffer);
-	offset = car_get_var(g_offset);
-	len = car_get_var(g_line_offset);
+	line_buffer = car_get_var_ptr(line_buffer);
+	offset = car_get_var(offset);
+	len = car_get_var(line_offset);
    region_size = region_device_sz(rdev);
line_buffer[len++] = c;
-	car_set_var(g_line_offset, len);
+	car_set_var(line_offset, len);
if (len >= LINE_BUFFER_SIZE ||
    	offset + len >= region_size || c == '\n') {
@@ -109,10 +109,10 @@
void flashconsole_tx_flush(void)
 {
-	const struct region_device *rdev = car_get_var(g_rdev_ptr);
-	uint8_t *line_buffer = car_get_var_ptr(g_line_buffer);
-	size_t offset = car_get_var(g_offset);
-	size_t len = car_get_var(g_line_offset);
+	const struct region_device *rdev = car_get_var(rdev_ptr);
+	uint8_t *line_buffer = car_get_var_ptr(line_buffer);
+	size_t offset = car_get_var(offset);
+	size_t len = car_get_var(line_offset);
    size_t region_size;
if (!rdev)
@@ -121,7 +121,7 @@
    /* Prevent any recursive loops in case the spi flash driver
     * calls printk (in case of transaction timeout or
     * any other error while writing) */
-	car_set_var(g_rdev_ptr, NULL);
+	car_set_var(rdev_ptr, NULL);
region_size = region_device_sz(rdev);
    if (offset + len >= region_size)
@@ -134,8 +134,8 @@
    if (offset + len >= region_size)
    	rdev = NULL;
-	car_set_var(g_offset, offset + len);
-	car_set_var(g_line_offset, 0);
+	car_set_var(offset, offset + len);
+	car_set_var(line_offset, 0);
-	car_set_var(g_rdev_ptr, rdev);
+	car_set_var(rdev_ptr, rdev);
 }
diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c
index d3d36c9..62d1bba 100644
--- a/src/drivers/spi/tpm/tpm.c
+++ b/src/drivers/spi/tpm/tpm.c
@@ -39,10 +39,10 @@
 #define CR50_TIMEOUT_INIT_MS 30000 /* Very long timeout for TPM init */
/* SPI slave structure for TPM device. */
-static struct spi_slave g_spi_slave;
+static struct spi_slave spi_slave;
/* Cached TPM device identification. */
-static struct tpm2_info g_tpm_info;
+static struct tpm2_info tpm_info;
/*
  * TODO(vbendeb): make CONFIG_DEBUG_TPM an int to allow different level of
@@ -60,7 +60,7 @@
void tpm2_get_info(struct tpm2_info *info)
 {
-	*info = g_tpm_info;
+	*info = tpm_info;
 }
__weak int tis_plat_irq_status(void)
@@ -133,9 +133,9 @@
if (wakeup_needed) {
    	/* Just in case Cr50 is asleep. */
-		spi_claim_bus(&g_spi_slave);
+		spi_claim_bus(&spi_slave);
    	udelay(1);
-		spi_release_bus(&g_spi_slave);
+		spi_release_bus(&spi_slave);
    	udelay(100);
    }
@@ -158,7 +158,7 @@
    	header.body[i + 1] = (addr >> (8 * (2 - i))) & 0xff;
/* CS assert wakes up the slave. */
-	spi_claim_bus(&g_spi_slave);
+	spi_claim_bus(&spi_slave);
/*
     * The TCG TPM over SPI specification introduces the notion of SPI
@@ -185,7 +185,7 @@
     * to require to stall the master, this would present an issue.
     * crosbug.com/p/52132 has been opened to track this.
     */
-	spi_xfer(&g_spi_slave, header.body, sizeof(header.body), NULL, 0);
+	spi_xfer(&spi_slave, header.body, sizeof(header.body), NULL, 0);
/*
     * Now poll the bus until TPM removes the stall bit. Give it up to 100
@@ -196,10 +196,10 @@
    do {
    	if (stopwatch_expired(&sw)) {
    		printk(BIOS_ERR, "TPM flow control failure\n");
-			spi_release_bus(&g_spi_slave);
+			spi_release_bus(&spi_slave);
    		return 0;
    	}
-		spi_xfer(&g_spi_slave, NULL, 0, &byte, 1);
+		spi_xfer(&spi_slave, NULL, 0, &byte, 1);
    } while (!(byte & 1));
    return 1;
 }
@@ -267,7 +267,7 @@
  */
 static void write_bytes(const void *buffer, size_t bytes)
 {
-	spi_xfer(&g_spi_slave, buffer, bytes, NULL, 0);
+	spi_xfer(&spi_slave, buffer, bytes, NULL, 0);
 }
/*
@@ -276,7 +276,7 @@
  */
 static void read_bytes(void *buffer, size_t bytes)
 {
-	spi_xfer(&g_spi_slave, NULL, 0, buffer, bytes);
+	spi_xfer(&spi_slave, NULL, 0, buffer, bytes);
 }
/*
@@ -291,7 +291,7 @@
    if (!start_transaction(false, bytes, reg_number))
    	return 0;
    write_bytes(buffer, bytes);
-	spi_release_bus(&g_spi_slave);
+	spi_release_bus(&spi_slave);
    return 1;
 }
@@ -309,7 +309,7 @@
    	return 0;
    }
    read_bytes(buffer, bytes);
-	spi_release_bus(&g_spi_slave);
+	spi_release_bus(&spi_slave);
    trace_dump("R", reg_number, bytes, buffer, 0);
    return 1;
 }
@@ -417,7 +417,7 @@
    uint8_t cmd;
    int retries;
-	memcpy(&g_spi_slave, spi_if, sizeof(*spi_if));
+	memcpy(&spi_slave, spi_if, sizeof(*spi_if));
/* clear any pending IRQs */
    tis_plat_irq_status();
@@ -474,15 +474,15 @@
     * structure.
     */
    tpm2_read_reg(TPM_RID_REG, &cmd, sizeof(cmd));
-	g_tpm_info.vendor_id = did_vid & 0xffff;
-	g_tpm_info.device_id = did_vid >> 16;
-	g_tpm_info.revision = cmd;
+	tpm_info.vendor_id = did_vid & 0xffff;
+	tpm_info.device_id = did_vid >> 16;
+	tpm_info.revision = cmd;
printk(BIOS_INFO, "Connected to device vid:did:rid of %4.4x:%4.4x:%2.2x\n",
-	       g_tpm_info.vendor_id, g_tpm_info.device_id, g_tpm_info.revision);
+	       tpm_info.vendor_id, tpm_info.device_id, tpm_info.revision);
/* Let's report device FW version if available. */
-	if (g_tpm_info.vendor_id == 0x1ae0) {
+	if (tpm_info.vendor_id == 0x1ae0) {
    	int chunk_count = 0;
    	size_t chunk_size;
    	/*
@@ -611,7 +611,7 @@
    const int HEADER_SIZE = 6;
/* Do not try using an uninitialized TPM. */
-	if (!g_tpm_info.vendor_id)
+	if (!tpm_info.vendor_id)
    	return 0;
/* Skip the two byte tag, read the size field. */
diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c
index b81a719..ab77a01 100644
--- a/src/drivers/vpd/vpd.c
+++ b/src/drivers/vpd/vpd.c
@@ -23,7 +23,7 @@
    int matched;
 };
-struct vpd_blob g_vpd_blob;
+struct vpd_blob vpd_blob;
/*
  * returns the size of data in a VPD 2.0 formatted fmap region, or 0.
@@ -85,10 +85,10 @@
    if (ro_vpd_size == 0 && rw_vpd_size == 0)
    	return;
-	g_vpd_blob.ro_base = NULL;
-	g_vpd_blob.ro_size = 0;
-	g_vpd_blob.rw_base = NULL;
-	g_vpd_blob.rw_size = 0;
+	vpd_blob.ro_base = NULL;
+	vpd_blob.ro_size = 0;
+	vpd_blob.rw_base = NULL;
+	vpd_blob.rw_size = 0;
struct region_device vpd;
@@ -101,9 +101,9 @@
    	}
    	rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET,
    		region_device_sz(&vpd) - GOOGLE_VPD_2_0_OFFSET);
-		g_vpd_blob.ro_base = (uint8_t *)(rdev_mmap_full(&vpd) +
+		vpd_blob.ro_base = (uint8_t *)(rdev_mmap_full(&vpd) +
    		sizeof(struct google_vpd_info));
-		g_vpd_blob.ro_size = ro_vpd_size;
+		vpd_blob.ro_size = ro_vpd_size;
    }
    if (rw_vpd_size) {
    	if (fmap_locate_area_as_rdev("RW_VPD", &vpd)) {
@@ -114,19 +114,19 @@
    	}
    	rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET,
    		region_device_sz(&vpd) - GOOGLE_VPD_2_0_OFFSET);
-		g_vpd_blob.rw_base = (uint8_t *)(rdev_mmap_full(&vpd) +
+		vpd_blob.rw_base = (uint8_t *)(rdev_mmap_full(&vpd) +
    		sizeof(struct google_vpd_info));
-		g_vpd_blob.rw_size = rw_vpd_size;
+		vpd_blob.rw_size = rw_vpd_size;
    }
-	g_vpd_blob.initialized = true;
+	vpd_blob.initialized = true;
 }
const struct vpd_blob *vpd_load_blob(void)
 {
-	if (g_vpd_blob.initialized == false)
+	if (vpd_blob.initialized == false)
    	vpd_get_blob();
-	return &g_vpd_blob;
+	return &vpd_blob;
 }
static int vpd_gets_callback(const uint8_t *key, uint32_t key_len,
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 0ce2f1a..6ebc291 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -148,19 +148,19 @@
  */
 void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads)
 {
-	static const struct pad_config *g_cfg;
-	static size_t g_num_pads;
+	static const struct pad_config *cfg;
+	static size_t num_pads;
/*
     * If cfg and num_pads are passed in from mainboard, maintain a
     * reference to the GPIO table.
     */
    if ((cfg == NULL) || (num_pads == 0)) {
-		cfg = g_cfg;
-		num_pads = g_num_pads;
+		cfg = cfg;
+		num_pads = num_pads;
    } else {
-		g_cfg = cfg;
-		g_num_pads = num_pads;
+		cfg = cfg;
+		num_pads = num_pads;
    }
gpio_configure_pads(cfg, num_pads);
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 5eb3761..9921825 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -88,7 +88,7 @@
static struct cse_device {
    uintptr_t sec_bar;
-} g_cse;
+} cse;
/*
  * Initialize the device with provided temporary BAR. If BAR is 0 use a
@@ -105,7 +105,7 @@
    u8 pcireg;
/* Assume it is already initialized, nothing else to do */
-	if (g_cse.sec_bar)
+	if (cse.sec_bar)
    	return;
/* Use default pre-ram bar */
@@ -127,7 +127,7 @@
    pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
    pci_write_config8(dev, PCI_COMMAND, pcireg);
-	g_cse.sec_bar = tempbar;
+	cse.sec_bar = tempbar;
 }
/* Get HECI BAR 0 from PCI configuration space */
@@ -147,17 +147,17 @@
 static uint32_t read_bar(uint32_t offset)
 {
    /* Reach PCI config space to get BAR in case CAR global not available */
-	if (!g_cse.sec_bar)
-		g_cse.sec_bar = get_cse_bar();
-	return read32((void *)(g_cse.sec_bar + offset));
+	if (!cse.sec_bar)
+		cse.sec_bar = get_cse_bar();
+	return read32((void *)(cse.sec_bar + offset));
 }
static void write_bar(uint32_t offset, uint32_t val)
 {
    /* Reach PCI config space to get BAR in case CAR global not available */
-	if (!g_cse.sec_bar)
-		g_cse.sec_bar = get_cse_bar();
-	return write32((void *)(g_cse.sec_bar + offset), val);
+	if (!cse.sec_bar)
+		cse.sec_bar = get_cse_bar();
+	return write32((void *)(cse.sec_bar + offset), val);
 }
static uint32_t read_cse_csr(void)
@@ -725,7 +725,7 @@
static void update_sec_bar(struct device *dev)
 {
-	g_cse.sec_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base;
+	cse.sec_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base;
 }
static void cse_set_resources(struct device *dev)
diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c
index 0e9553c..3ca0e13 100644
--- a/src/soc/nvidia/tegra/i2c.c
+++ b/src/soc/nvidia/tegra/i2c.c
@@ -193,7 +193,7 @@
    struct i2c_msg *seg = segments;
    int i;
-	if (bus >= g_num_i2c_buses) {
+	if (bus >= num_i2c_buses) {
    	printk(BIOS_ERR, "%s: ERROR: invalid I2C bus (%u)\n", __func__,
    	       bus);
    	return -1;
@@ -212,7 +212,7 @@
 {
    struct tegra_i2c_regs *regs;
-	if (bus >= g_num_i2c_buses) {
+	if (bus >= num_i2c_buses) {
    	printk(BIOS_ERR, "%s: ERROR: invalid I2C bus (%u)\n", __func__,
    	       bus);
    	return;
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 4974e08c..cf67817 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -111,7 +111,7 @@
    uint8_t fpr_max;
 };
-static struct ich_spi_controller g_cntlr;
+static struct ich_spi_controller cntlr;
enum {
    SPIS_SCIP =		0x0001,
@@ -260,9 +260,9 @@
    uint32_t ichspi_bbar;
minaddr &= bbar_mask;
-	ichspi_bbar = readl_(g_cntlr.bbar) & ~bbar_mask;
+	ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask;
    ichspi_bbar |= minaddr;
-	writel_(ichspi_bbar, g_cntlr.bbar);
+	writel_(ichspi_bbar, cntlr.bbar);
 }
#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
@@ -305,42 +305,42 @@
if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
    	ich7_spi = get_spi_bar(dev);
-		g_cntlr.ich7_spi = ich7_spi;
-		g_cntlr.opmenu = ich7_spi->opmenu;
-		g_cntlr.menubytes = sizeof(ich7_spi->opmenu);
-		g_cntlr.optype = &ich7_spi->optype;
-		g_cntlr.addr = &ich7_spi->spia;
-		g_cntlr.data = (uint8_t *)ich7_spi->spid;
-		g_cntlr.databytes = sizeof(ich7_spi->spid);
-		g_cntlr.status = (uint8_t *)&ich7_spi->spis;
-		g_cntlr.control = &ich7_spi->spic;
-		g_cntlr.bbar = &ich7_spi->bbar;
-		g_cntlr.preop = &ich7_spi->preop;
-		g_cntlr.fpr = &ich7_spi->pbr[0];
-		g_cntlr.fpr_max = 3;
+		cntlr.ich7_spi = ich7_spi;
+		cntlr.opmenu = ich7_spi->opmenu;
+		cntlr.menubytes = sizeof(ich7_spi->opmenu);
+		cntlr.optype = &ich7_spi->optype;
+		cntlr.addr = &ich7_spi->spia;
+		cntlr.data = (uint8_t *)ich7_spi->spid;
+		cntlr.databytes = sizeof(ich7_spi->spid);
+		cntlr.status = (uint8_t *)&ich7_spi->spis;
+		cntlr.control = &ich7_spi->spic;
+		cntlr.bbar = &ich7_spi->bbar;
+		cntlr.preop = &ich7_spi->preop;
+		cntlr.fpr = &ich7_spi->pbr[0];
+		cntlr.fpr_max = 3;
    } else {
    	ich9_spi = get_spi_bar(dev);
-		g_cntlr.ich9_spi = ich9_spi;
+		cntlr.ich9_spi = ich9_spi;
    	hsfs = readw_(&ich9_spi->hsfs);
-		g_cntlr.hsfs = hsfs;
-		g_cntlr.opmenu = ich9_spi->opmenu;
-		g_cntlr.menubytes = sizeof(ich9_spi->opmenu);
-		g_cntlr.optype = &ich9_spi->optype;
-		g_cntlr.addr = &ich9_spi->faddr;
-		g_cntlr.data = (uint8_t *)ich9_spi->fdata;
-		g_cntlr.databytes = sizeof(ich9_spi->fdata);
-		g_cntlr.status = &ich9_spi->ssfs;
-		g_cntlr.control = (uint16_t *)ich9_spi->ssfc;
-		g_cntlr.bbar = &ich9_spi->bbar;
-		g_cntlr.preop = &ich9_spi->preop;
-		g_cntlr.fpr = &ich9_spi->pr[0];
-		g_cntlr.fpr_max = 5;
+		cntlr.hsfs = hsfs;
+		cntlr.opmenu = ich9_spi->opmenu;
+		cntlr.menubytes = sizeof(ich9_spi->opmenu);
+		cntlr.optype = &ich9_spi->optype;
+		cntlr.addr = &ich9_spi->faddr;
+		cntlr.data = (uint8_t *)ich9_spi->fdata;
+		cntlr.databytes = sizeof(ich9_spi->fdata);
+		cntlr.status = &ich9_spi->ssfs;
+		cntlr.control = (uint16_t *)ich9_spi->ssfc;
+		cntlr.bbar = &ich9_spi->bbar;
+		cntlr.preop = &ich9_spi->preop;
+		cntlr.fpr = &ich9_spi->pr[0];
+		cntlr.fpr_max = 5;
-		if (g_cntlr.hsfs & HSFS_FDV) {
+		if (cntlr.hsfs & HSFS_FDV) {
    		writel_(4, &ich9_spi->fdoc);
-			g_cntlr.flmap0 = readl_(&ich9_spi->fdod);
+			cntlr.flmap0 = readl_(&ich9_spi->fdod);
    		writel_(0x1000, &ich9_spi->fdoc);
-			g_cntlr.flcomp = readl_(&ich9_spi->fdod);
+			cntlr.flcomp = readl_(&ich9_spi->fdod);
    	}
    }
@@ -358,9 +358,9 @@
 static int spi_locked(void)
 {
    if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
-		return !!(readw_(&g_cntlr.ich7_spi->spis) & HSFS_FLOCKDN);
+		return !!(readw_(&cntlr.ich7_spi->spis) & HSFS_FLOCKDN);
    } else {
-		return !!(readw_(&g_cntlr.ich9_spi->hsfs) & HSFS_FLOCKDN);
+		return !!(readw_(&cntlr.ich9_spi->hsfs) & HSFS_FLOCKDN);
    }
 }
@@ -436,10 +436,10 @@
    spi_use_out(trans, 1);
    if (!spi_locked()) {
    	/* The lock is off, so just use index 0. */
-		writeb_(trans->opcode, g_cntlr.opmenu);
-		optypes = readw_(g_cntlr.optype);
+		writeb_(trans->opcode, cntlr.opmenu);
+		optypes = readw_(cntlr.optype);
    	optypes = (optypes & 0xfffc) | (trans->type & 0x3);
-		writew_(optypes, g_cntlr.optype);
+		writew_(optypes, cntlr.optype);
    	return 0;
    }
@@ -451,7 +451,7 @@
    if (trans->opcode == SPI_OPCODE_WREN)
    	return 0;
-	read_reg(g_cntlr.opmenu, opmenu, sizeof(opmenu));
+	read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
    for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) {
    	if (opmenu[opcode_index] == trans->opcode)
    		break;
@@ -463,7 +463,7 @@
    	return -1;
    }
-	optypes = readw_(g_cntlr.optype);
+	optypes = readw_(cntlr.optype);
    optype = (optypes >> (opcode_index * 2)) & 0x3;
    if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
    	optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
@@ -512,10 +512,10 @@
    u16 status = 0;
while (timeout--) {
-		status = readw_(g_cntlr.status);
+		status = readw_(cntlr.status);
    	if (wait_til_set ^ ((status & bitmask) == 0)) {
    		if (wait_til_set)
-				writew_((status & bitmask), g_cntlr.status);
+				writew_((status & bitmask), cntlr.status);
    		return status;
    	}
    	udelay(10);
@@ -528,9 +528,9 @@
static int spi_is_multichip(void)
 {
-	if (!(g_cntlr.hsfs & HSFS_FDV))
+	if (!(cntlr.hsfs & HSFS_FDV))
    	return 0;
-	return !!((g_cntlr.flmap0 >> 8) & 3);
+	return !!((cntlr.flmap0 >> 8) & 3);
 }
static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
@@ -561,7 +561,7 @@
    if (ich_status_poll(SPIS_SCIP, 0) == -1)
    	return -1;
-	writew_(SPIS_CDS | SPIS_FCERR, g_cntlr.status);
+	writew_(SPIS_CDS | SPIS_FCERR, cntlr.status);
spi_setup_type(&trans);
    if ((opcode_index = spi_setup_opcode(&trans)) < 0)
@@ -576,7 +576,7 @@
    	 * issuing a transaction between WREN and DATA.
    	 */
    	if (!spi_locked())
-			writew_(trans.opcode, g_cntlr.preop);
+			writew_(trans.opcode, cntlr.preop);
    	return 0;
    }
@@ -584,13 +584,13 @@
    control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
/* Issue atomic preop cycle if needed */
-	if (readw_(g_cntlr.preop))
+	if (readw_(cntlr.preop))
    	control |= SPIC_ACS;
if (!trans.bytesout && !trans.bytesin) {
    	/* SPI addresses are 24 bit only */
    	if (with_address)
-			writel_(trans.offset & 0x00FFFFFF, g_cntlr.addr);
+			writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
/*
    	 * This is a 'no data' command (like Write Enable), its
@@ -598,7 +598,7 @@
    	 * spi_setup_opcode() above. Tell the chip to send the
    	 * command.
    	 */
-		writew_(control, g_cntlr.control);
+		writew_(control, cntlr.control);
/* wait for the result */
    	status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
@@ -620,7 +620,7 @@
     * and followed by other SPI commands, and this sequence is controlled
     * by the SPI chip driver.
     */
-	if (trans.bytesout > g_cntlr.databytes) {
+	if (trans.bytesout > cntlr.databytes) {
    	printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use"
    	     " spi_crop_chunk()?\n");
    	return -1;
@@ -634,28 +634,28 @@
    	uint32_t data_length;
/* SPI addresses are 24 bit only */
-		writel_(trans.offset & 0x00FFFFFF, g_cntlr.addr);
+		writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
if (trans.bytesout)
-			data_length = min(trans.bytesout, g_cntlr.databytes);
+			data_length = min(trans.bytesout, cntlr.databytes);
    	else
-			data_length = min(trans.bytesin, g_cntlr.databytes);
+			data_length = min(trans.bytesin, cntlr.databytes);
/* Program data into FDATA0 to N */
    	if (trans.bytesout) {
-			write_reg(trans.out, g_cntlr.data, data_length);
+			write_reg(trans.out, cntlr.data, data_length);
    		spi_use_out(&trans, data_length);
    		if (with_address)
    			trans.offset += data_length;
    	}
/* Add proper control fields' values */
-		control &= ~((g_cntlr.databytes - 1) << 8);
+		control &= ~((cntlr.databytes - 1) << 8);
    	control |= SPIC_DS;
    	control |= (data_length - 1) << 8;
/* write it */
-		writew_(control, g_cntlr.control);
+		writew_(control, cntlr.control);
/* Wait for Cycle Done Status or Flash Cycle Error. */
    	status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
@@ -668,7 +668,7 @@
    	}
if (trans.bytesin) {
-			read_reg(g_cntlr.data, trans.in, data_length);
+			read_reg(cntlr.data, trans.in, data_length);
    		spi_use_in(&trans, data_length);
    		if (with_address)
    			trans.offset += data_length;
@@ -677,7 +677,7 @@
spi_xfer_exit:
    /* Clear atomic preop now that xfer is done */
-	writew_(0, g_cntlr.preop);
+	writew_(0, cntlr.preop);
return 0;
 }
@@ -685,9 +685,9 @@
 /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
 static void ich_hwseq_set_addr(uint32_t addr)
 {
-	uint32_t addr_old = readl_(&g_cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
+	uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
-	writel_((addr & 0x01FFFFFF) | addr_old, &g_cntlr.ich9_spi->faddr);
+	writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr);
 }
/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
@@ -701,17 +701,17 @@
    uint32_t addr;
timeout /= 8; /* scale timeout duration to counter */
-	while ((((hsfs = readw_(&g_cntlr.ich9_spi->hsfs)) &
+	while ((((hsfs = readw_(&cntlr.ich9_spi->hsfs)) &
    	 (HSFS_FDONE | HSFS_FCERR)) == 0) &&
           --timeout) {
    	udelay(8);
    }
-	writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs);
+	writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
if (!timeout) {
    	uint16_t hsfc;
-		addr = readl_(&g_cntlr.ich9_spi->faddr) & 0x01FFFFFF;
-		hsfc = readw_(&g_cntlr.ich9_spi->hsfc);
+		addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+		hsfc = readw_(&cntlr.ich9_spi->hsfc);
    	printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and "
    	       "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",
    	       addr, addr + len - 1, addr, len - 1,
@@ -721,8 +721,8 @@
if (hsfs & HSFS_FCERR) {
    	uint16_t hsfc;
-		addr = readl_(&g_cntlr.ich9_spi->faddr) & 0x01FFFFFF;
-		hsfc = readw_(&g_cntlr.ich9_spi->hsfc);
+		addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF;
+		hsfc = readw_(&cntlr.ich9_spi->hsfc);
    	printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
    	       "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",
    	       addr, addr + len - 1, addr, len - 1,
@@ -758,17 +758,17 @@
while (offset < end) {
    	/* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
-		writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs);
+		writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
ich_hwseq_set_addr(offset);
offset += erase_size;
-		hsfc = readw_(&g_cntlr.ich9_spi->hsfc);
+		hsfc = readw_(&cntlr.ich9_spi->hsfc);
    	hsfc &= ~HSFC_FCYCLE; /* clear operation */
    	hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
    	hsfc |= HSFC_FGO; /* start */
-		writew_(hsfc, &g_cntlr.ich9_spi->hsfc);
+		writew_(hsfc, &cntlr.ich9_spi->hsfc);
    	if (ich_hwseq_wait_for_cycle_complete(timeout, len)) {
    		printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);
    		ret = -1;
@@ -790,7 +790,7 @@
for (i = 0; i < len; i++) {
    	if ((i % 4) == 0)
-			temp32 = readl_(g_cntlr.data + i);
+			temp32 = readl_(cntlr.data + i);
data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
    }
@@ -812,20 +812,20 @@
    }
/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
-	writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs);
+	writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
while (len > 0) {
-		block_len = min(len, g_cntlr.databytes);
+		block_len = min(len, cntlr.databytes);
    	if (block_len > (~addr & 0xff))
    		block_len = (~addr & 0xff) + 1;
    	ich_hwseq_set_addr(addr);
-		hsfc = readw_(&g_cntlr.ich9_spi->hsfc);
+		hsfc = readw_(&cntlr.ich9_spi->hsfc);
    	hsfc &= ~HSFC_FCYCLE; /* set read operation */
    	hsfc &= ~HSFC_FDBC; /* clear byte count */
    	/* set byte count */
    	hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
    	hsfc |= HSFC_FGO; /* start */
-		writew_(hsfc, &g_cntlr.ich9_spi->hsfc);
+		writew_(hsfc, &cntlr.ich9_spi->hsfc);
if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
    		return 1;
@@ -857,11 +857,11 @@
    	temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
-			writel_(temp32, g_cntlr.data + (i - (i % 4)));
+			writel_(temp32, cntlr.data + (i - (i % 4)));
    }
    i--;
    if ((i % 4) != 3) /* Write remaining data to regs. */
-		writel_(temp32, g_cntlr.data + (i - (i % 4)));
+		writel_(temp32, cntlr.data + (i - (i % 4)));
 }
static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
@@ -880,24 +880,24 @@
    }
/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
-	writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs);
+	writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
while (len > 0) {
-		block_len = min(len, g_cntlr.databytes);
+		block_len = min(len, cntlr.databytes);
    	if (block_len > (~addr & 0xff))
    		block_len = (~addr & 0xff) + 1;
ich_hwseq_set_addr(addr);
ich_fill_data(buf, block_len);
-		hsfc = readw_(&g_cntlr.ich9_spi->hsfc);
+		hsfc = readw_(&cntlr.ich9_spi->hsfc);
    	hsfc &= ~HSFC_FCYCLE; /* clear operation */
    	hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
    	hsfc &= ~HSFC_FDBC; /* clear byte count */
    	/* set byte count */
    	hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
    	hsfc |= HSFC_FGO; /* start */
-		writew_(hsfc, &g_cntlr.ich9_spi->hsfc);
+		writew_(hsfc, &cntlr.ich9_spi->hsfc);
if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) {
    		printk(BIOS_ERR, "SF: write failure at %x\n",
@@ -934,7 +934,7 @@
    flash->name = "Opaque HW-sequencing";
ich_hwseq_set_addr(0);
-	switch ((g_cntlr.hsfs >> 3) & 3) {
+	switch ((cntlr.hsfs >> 3) & 3) {
    case 0:
    	flash->sector_size = 256;
    	break;
@@ -949,12 +949,12 @@
    	break;
    }
-	flash->size = 1 << (19 + (g_cntlr.flcomp & 7));
+	flash->size = 1 << (19 + (cntlr.flcomp & 7));
flash->ops = &spi_flash_ops;
-	if ((g_cntlr.hsfs & HSFS_FDV) && ((g_cntlr.flmap0 >> 8) & 3))
-		flash->size += 1 << (19 + ((g_cntlr.flcomp >> 3) & 7));
+	if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3))
+		flash->size += 1 << (19 + ((cntlr.flcomp >> 3) & 7));
    printk(BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
return 0;
@@ -1008,16 +1008,16 @@
    int fpr;
    uint32_t *fpr_base;
-	fpr_base = g_cntlr.fpr;
+	fpr_base = cntlr.fpr;
/* Find first empty FPR */
-	for (fpr = 0; fpr < g_cntlr.fpr_max; fpr++) {
+	for (fpr = 0; fpr < cntlr.fpr_max; fpr++) {
    	reg = read32(&fpr_base[fpr]);
    	if (reg == 0)
    		break;
    }
-	if (fpr == g_cntlr.fpr_max) {
+	if (fpr == cntlr.fpr_max) {
    	printk(BIOS_ERR, "ERROR: No SPI FPR free!\n");
    	return -1;
    }
@@ -1106,12 +1106,12 @@
spi_opprefix = spi_config->opprefixes[0]
    	| (spi_config->opprefixes[1] << 8);
-	writew_(spi_opprefix, g_cntlr.preop);
+	writew_(spi_opprefix, cntlr.preop);
    for (i = 0; i < ARRAY_SIZE(spi_config->ops); i++) {
    	optype |= (spi_config->ops[i].type & 3) << (i * 2);
-		writeb_(spi_config->ops[i].op, &g_cntlr.opmenu[i]);
+		writeb_(spi_config->ops[i].op, &cntlr.opmenu[i]);
    }
-	writew_(optype, g_cntlr.optype);
+	writew_(optype, cntlr.optype);
 }
__weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config)
diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c
index 7eef2d1..3946e44 100644
--- a/src/vendorcode/google/chromeos/ramoops.c
+++ b/src/vendorcode/google/chromeos/ramoops.c
@@ -63,11 +63,11 @@
  * the pointer to the chromeos_acpi_t structure is needed to update the
  * fields with the rserved base and size.
  */
-static chromeos_acpi_t *g_chromeos;
+static chromeos_acpi_t *chromeos;
static void set_global_chromeos_pointer(chromeos_acpi_t *chromeos)
 {
-	g_chromeos = chromeos;
+	chromeos = chromeos;
 }
static void update_gnvs(void *arg)
@@ -77,7 +77,7 @@
    set_ramoops(*chromeos, (void *)ramoops_base, ramoops_size);
 }
-static BOOT_STATE_CALLBACK(bscb_ramoops, update_gnvs, &g_chromeos);
+static BOOT_STATE_CALLBACK(bscb_ramoops, update_gnvs, &chromeos);
void chromeos_reserve_ram_oops(struct device *dev, int idx)
 {
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4936ff9780a0d3ed9b8b539772bc48887f8d5eed
Gerrit-Change-Number: 37358
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi pgeorgi@google.com
Gerrit-MessageType: newchange



    