Change in coreboot[master]: soc/intel/alderlake: Add ADLP 4+4+2 power configurations

[Curtis Chen (Code Review)]

Attention is currently required from: Curtis Chen, Patrick Rudolph.
Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/59483

to look at the new patch set (#5).

Change subject: soc/intel/alderlake: Add ADLP 4+4+2 power configurations
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soc/intel/alderlake: Add ADLP 4+4+2 power configurations

Map existing PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADLP 4+4+2 45W SKU power
related settings.
Per doc#626774 ADL_MOW_WW46_2021, update PD optimization relaxation for
ADL-P 482(28W) and 442(45W).

BUG=b:193864533
TEST=Build and check fsp log to confirm the settings are set properly.

Signed-off-by: Curtis Chen 
Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/chipset.cb
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/vr_config.c
4 files changed, 18 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/59483/5