[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Update eMMC DLL settings

[Dtrain Hsu (Code Review)]

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86016?usp=email )

Change subject: mb/trulo/var/uldrenite: Update eMMC DLL settings
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mb/trulo/var/uldrenite: Update eMMC DLL settings

Based on Intel eMMC tuning result, update eMMC DLL settings.

BUG=b:388438199
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I276ebbfc29e3899cbacdc2353648017a3fa5b8a6
Signed-off-by: Dtrain Hsu 
---
M src/mainboard/google/brya/variants/uldrenite/overridetree.cb
1 file changed, 5 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/86016/1

diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index e5c98c4..f7ff776 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -26,7 +26,7 @@
    # Refer to EDS-Vol2-42.3.8.
    # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
    # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
-	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x311b"

# EMMC TX DATA Delay 2
    # Refer to EDS-Vol2-42.3.9.
@@ -34,7 +34,7 @@
    # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
    # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
    # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
-	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C282928"

# EMMC RX CMD/DATA Delay 1
    # Refer to EDS-Vol2-42.3.10.
@@ -42,7 +42,7 @@
    # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
    # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
    # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
-	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C19593B"

# EMMC RX CMD/DATA Delay 2
    # Refer to EDS-Vol2-42.3.12.
@@ -53,13 +53,13 @@
    #         11: Reserved
    # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
    # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
-	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004E"
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10026"

# EMMC Rx Strobe Delay
    # Refer to EDS-Vol2-42.3.11.
    # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
    # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
-	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
+	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01313"

register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
    register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1