Change in coreboot[master]: soc/amd/cezanne: Enable early LPC support in bootblock stage

[Bao Zheng (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Zheng Bao, Felix Held.
Hello Zheng Bao,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/49929

to review the following change.

Change subject: soc/amd/cezanne: Enable early LPC support in bootblock stage
......................................................................

soc/amd/cezanne: Enable early LPC support in bootblock stage

Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767
Signed-off-by: Zheng Bao 
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/early_fch.c
M src/soc/amd/cezanne/include/soc/iomap.h
M src/soc/amd/cezanne/include/soc/southbridge.h
4 files changed, 38 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/49929/1

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 9b76673..23e55d1 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -24,6 +24,7 @@
    select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
    select SOC_AMD_COMMON_BLOCK_NONCAR
    select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
+	select SOC_AMD_COMMON_BLOCK_LPC
    select SOC_AMD_COMMON_BLOCK_SMBUS
    select SOC_AMD_COMMON_BLOCK_SMI
    select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index 37ba4c7..8353cb1 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <amdblocks/acpimmio.h>
+#include <amdblocks/lpc.h>
 #include <amdblocks/smbus.h>
 #include <console/console.h>
 #include <soc/southbridge.h>
@@ -9,6 +10,8 @@
 /* Before console init */
 void fch_pre_init(void)
 {
+	lpc_early_init();
+
    enable_acpimmio_decode_pm04();
    fch_smbus_init();
    fch_enable_cf9_io();
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h
index 20f7037..a9fc789 100644
--- a/src/soc/amd/cezanne/include/soc/iomap.h
+++ b/src/soc/amd/cezanne/include/soc/iomap.h
@@ -3,6 +3,8 @@
 #ifndef AMD_CEZANNE_IOMAP_H
 #define AMD_CEZANNE_IOMAP_H

+
+#define SPI_BASE_ADDRESS		0xfec10000
 /* FCH AL2AHB Registers */
 #define ALINK_AHB_ADDRESS		0xfedc0000

@@ -11,6 +13,20 @@
 #define APU_UART0_BASE			0xfedc9000
 #define APU_UART1_BASE			0xfedca000

+#define I2C_MASTER_DEV_COUNT		4
+#define I2C_MASTER_START_INDEX		2
+#define I2C_SLAVE_DEV_COUNT		1
+
+#define APU_I2C2_BASE			0xfedc4000
+#define APU_I2C3_BASE			0xfedc5000
+#define APU_I2C4_BASE			0xfedc6000
+
+/* I2C parameters for lpc_read_resources */
+#define I2C_BASE_ADDRESS		APU_I2C2_BASE
+#define I2C_DEVICE_SIZE			0x00001000
+#define I2C_DEVICE_COUNT		(I2C_MASTER_DEV_COUNT \
+					 - I2C_MASTER_START_INDEX)
+
 /* MMIO Ranges */
 #define FLASH_BASE_ADDR			((0xffffffff - CONFIG_ROM_SIZE) + 1)

diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index 2a294e9..e632f28 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -8,8 +8,26 @@
 /* Power management registers:  0xfed80300 or index/data at IO 0xcd6/cd7 */
 #define PWR_RESET_CFG			0x10
 #define   TOGGLE_ALL_PWR_GOOD		(1 << 1)
+
+#define PM_SERIRQ_CONF			0x54
+#define   PM_SERIRQ_NUM_BITS_17		0x0000
+#define   PM_SERIRQ_NUM_BITS_18		0x0004
+#define   PM_SERIRQ_NUM_BITS_19		0x0008
+#define   PM_SERIRQ_NUM_BITS_20		0x000c
+#define   PM_SERIRQ_NUM_BITS_21		0x0010
+#define   PM_SERIRQ_NUM_BITS_22		0x0014
+#define   PM_SERIRQ_NUM_BITS_23		0x0018
+#define   PM_SERIRQ_NUM_BITS_24		0x001c
+#define   PM_SERIRQ_MODE		BIT(6)
+#define   PM_SERIRQ_ENABLE		BIT(7)
+
 #define PM_ACPI_SMI_CMD			0x6a

+#define PM_LPC_GATING			0xec
+#define   PM_LPC_AB_NO_BYPASS_EN	BIT(2)
+#define   PM_LPC_A20_EN			BIT(1)
+#define   PM_LPC_ENABLE			BIT(0)
+
 #define FCH_LEGACY_UART_DECODE		(ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */

/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */