Change in ...coreboot[master]: soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33575
Change subject: soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE ......................................................................
soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE
What it really means to do is to use different FSP headers.
Change-Id: I3c75d4aac8525ab2639608fb9c1b3a9afef0e943 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/romstage/fsp_params.c 4 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/33575/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dac3522..7b4282c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -3,7 +3,7 @@ help Intel Cannonlake support
-config SOC_INTEL_COMMON_CANNONLAKE_BASE +config SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS bool default n select SOC_INTEL_CANNONLAKE @@ -11,7 +11,7 @@ Single Kconfig option to select common base Cannonlake support. This Kconfig will help to select majority of CNL SoC features. Major difference that exist today between - SOC_INTEL_COMMON_CANNONLAKE_BASE and SOC_INTEL_CANNONLAKE Kconfig + SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS and SOC_INTEL_CANNONLAKE Kconfig are in FSP Header Files. Hence this Kconfig might help to select required SoC support FSP headers. Any future Intel SoC would like to make use of CNL support might just select this Kconfig. @@ -19,21 +19,21 @@ config SOC_INTEL_COFFEELAKE bool default n - select SOC_INTEL_COMMON_CANNONLAKE_BASE + select SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS help Intel Coffeelake support
config SOC_INTEL_WHISKEYLAKE bool default n - select SOC_INTEL_COMMON_CANNONLAKE_BASE + select SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS help Intel Whiskeylake support
config SOC_INTEL_COMETLAKE bool default n - select SOC_INTEL_COMMON_CANNONLAKE_BASE + select SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS help Intel Cometlake support
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 0d51c1c..3b4c980 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -111,7 +111,7 @@ enum { SaGv_Disabled, SaGv_FixedLow, -#if !CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) +#if !CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS) SaGv_FixedMid, #endif SaGv_FixedHigh, diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index d98e2f5..7dae615 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -500,7 +500,7 @@ * have this check, where CNL CPU die is not based on KBL CPU * so skip this check for CNL. */ - if (!CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)) + if (!CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)) return 0;
/* diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 77bad8f..a1e3d76 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -69,7 +69,7 @@ /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
-#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) +#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS) m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; #endif
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33575 )
Change subject: soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33575 )
Change subject: soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE ......................................................................
soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE
What it really means to do is to use different FSP headers.
Change-Id: I3c75d4aac8525ab2639608fb9c1b3a9afef0e943 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/33575 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/romstage/fsp_params.c 4 files changed, 8 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dac3522..7b4282c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -3,7 +3,7 @@ help Intel Cannonlake support
-config SOC_INTEL_COMMON_CANNONLAKE_BASE +config SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS bool default n select SOC_INTEL_CANNONLAKE @@ -11,7 +11,7 @@ Single Kconfig option to select common base Cannonlake support. This Kconfig will help to select majority of CNL SoC features. Major difference that exist today between - SOC_INTEL_COMMON_CANNONLAKE_BASE and SOC_INTEL_CANNONLAKE Kconfig + SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS and SOC_INTEL_CANNONLAKE Kconfig are in FSP Header Files. Hence this Kconfig might help to select required SoC support FSP headers. Any future Intel SoC would like to make use of CNL support might just select this Kconfig. @@ -19,21 +19,21 @@ config SOC_INTEL_COFFEELAKE bool default n - select SOC_INTEL_COMMON_CANNONLAKE_BASE + select SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS help Intel Coffeelake support
config SOC_INTEL_WHISKEYLAKE bool default n - select SOC_INTEL_COMMON_CANNONLAKE_BASE + select SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS help Intel Whiskeylake support
config SOC_INTEL_COMETLAKE bool default n - select SOC_INTEL_COMMON_CANNONLAKE_BASE + select SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS help Intel Cometlake support
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 0d51c1c..3b4c980 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -111,7 +111,7 @@ enum { SaGv_Disabled, SaGv_FixedLow, -#if !CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) +#if !CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS) SaGv_FixedMid, #endif SaGv_FixedHigh, diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index d98e2f5..7dae615 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -500,7 +500,7 @@ * have this check, where CNL CPU die is not based on KBL CPU * so skip this check for CNL. */ - if (!CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)) + if (!CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)) return 0;
/* diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 77bad8f..a1e3d76 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -69,7 +69,7 @@ /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
-#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) +#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS) m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; #endif
-
Arthur Heymans (Code Review) -
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)