the following patch was just integrated into master: commit 780935687d74f89a25a9c58952314be6af61c348 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Tue Nov 11 17:22:23 2014 +0200
pcengines/apu1: Implement board GPIOs
Some GPIO pins are shared with (disabled) PCI bridge 0:14.4.
As our PCI subsystem currently does not configure PCI bridges that are marked disabled, but remain visible in the hardware, we cannot mark 0:14.4 disabled in devicetree just yet.
Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: http://review.coreboot.org/8326 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc mr.nuke.me@gmail.com
See http://review.coreboot.org/8326 for details.
-gerrit