Change in coreboot[master]: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates

[Shreesh Chhabbi (Code Review)]

Attention is currently required from: Furquan Shaikh, Shreesh Chhabbi.
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 )

Change subject: soc/intel/tgl: Disable S0i3.2 & S0i3.3 substates
......................................................................

Patch Set 4:

(1 comment)

This change is ready for review.

File src/soc/intel/tigerlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/49766/comment/bd0ef2b3_988a4bbe 
PS3, Line 236: LpmStateEnableMask
> I think we can probably do this: […]

Hi Furquan, I did not find the upds for external bypass, external clk gate and external phy gate. Are you suggesting to have these read from device tree and check their status to enable/disable substates?