Change in coreboot[master]: mb/supermicro: Add Supermicro X9SCL+-F - coreboot-gerrit

14 Aug 2019

Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34873 )
Change subject: mb/supermicro: Add Supermicro X9SCL+-F
......................................................................
mb/supermicro: Add Supermicro X9SCL+-F
This port is not working correctly at the moment as coreboot gets stuck
in or before postCAR.
What works:
- RAMinit
- Serial (RS232)
What does not work:
- basically everything else
Further notes:
- To prevent problems its recommended to always flash after powering the
power supply, disable and reenable power supply before flashing.
Change-Id: I9b4bf0f3caa2533b416637ce5baf4c4aad2ad94a
Signed-off-by: Christoph Pomaska c.pomaska@hosting.de
---
A src/mainboard/supermicro/x9scl-f/Kconfig
A src/mainboard/supermicro/x9scl-f/Kconfig.name
A src/mainboard/supermicro/x9scl-f/Makefile.inc
A src/mainboard/supermicro/x9scl-f/acpi/ec.asl
A src/mainboard/supermicro/x9scl-f/acpi/platform.asl
A src/mainboard/supermicro/x9scl-f/acpi/superio.asl
A src/mainboard/supermicro/x9scl-f/acpi_tables.c
A src/mainboard/supermicro/x9scl-f/board_info.txt
A src/mainboard/supermicro/x9scl-f/devicetree.cb
A src/mainboard/supermicro/x9scl-f/dsdt.asl
A src/mainboard/supermicro/x9scl-f/gpio.c
A src/mainboard/supermicro/x9scl-f/hda_verb.c
A src/mainboard/supermicro/x9scl-f/mainboard.c
A src/mainboard/supermicro/x9scl-f/romstage.c
14 files changed, 618 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34873/1

diff --git a/src/mainboard/supermicro/x9scl-f/Kconfig b/src/mainboard/supermicro/x9scl-f/Kconfig
new file mode 100644
index 0000000..f4bead2
--- /dev/null
+++ b/src/mainboard/supermicro/x9scl-f/Kconfig
@@ -0,0 +1,64 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Hosting.de GmbH
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+##
+
+if BOARD_SUPERMICRO_X9SCL_PLUS_F
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_INT15
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_BD82X6X
+	select USE_NATIVE_RAMINIT
+	select SUPERIO_NUVOTON_NCT6776
+	select SUPERIO_NUVOTON_NCT6776_COM_A
+	select SUPERIO_NUVOTON_WPCM450
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select NO_STAGE_CACHE
+
+config MAINBOARD_DIR
+	string
+	default "supermicro/x9scl-f"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "X9SCL+-F"
+
+config DRAM_RESET_GATE_GPIO # FIXME: check this
+	int
+	default 60
+
+config MAX_CPUS
+	int
+	default 8
+
+config VGA_BIOS_FILE
+	string
+	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vgabios.bin"
+
+config VGA_BIOS_ID
+	string
+	depends on VGA_BIOS
+	default "10sb,0532"
+
+config USBDEBUG_HCD_INDEX # FIXME: check this
+	int
+	default 2
+endif
diff --git a/src/mainboard/supermicro/x9scl-f/Kconfig.name b/src/mainboard/supermicro/x9scl-f/Kconfig.name
new file mode 100644
index 0000000..fd73657
--- /dev/null
+++ b/src/mainboard/supermicro/x9scl-f/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_SUPERMICRO_X9SCL_PLUS_F
+	bool "X9SCL+-F"
diff --git a/src/mainboard/supermicro/x9scl-f/Makefile.inc b/src/mainboard/supermicro/x9scl-f/Makefile.inc
new file mode 100644
index 0000000..3dae61e
--- /dev/null
+++ b/src/mainboard/supermicro/x9scl-f/Makefile.inc
@@ -0,0 +1 @@
+romstage-y += gpio.c
diff --git a/src/mainboard/supermicro/x9scl-f/acpi/ec.asl b/src/mainboard/supermicro/x9scl-f/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/supermicro/x9scl-f/acpi/ec.asl
diff --git a/src/mainboard/supermicro/x9scl-f/acpi/platform.asl b/src/mainboard/supermicro/x9scl-f/acpi/platform.asl
new file mode 100644
index 0000000..b269aa7
--- /dev/null
+++ b/src/mainboard/supermicro/x9scl-f/acpi/platform.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Hosting.de GmbH
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+}
diff --git a/src/mainboard/supermicro/x9scl-f/acpi/superio.asl b/src/mainboard/supermicro/x9scl-f/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/supermicro/x9scl-f/acpi/superio.asl
diff --git a/src/mainboard/supermicro/x9scl-f/acpi_tables.c b/src/mainboard/supermicro/x9scl-f/acpi_tables.c
new file mode 100644
index 0000000..315379d
--- /dev/null
+++ b/src/mainboard/supermicro/x9scl-f/acpi_tables.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2019 Hosting.de GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+/* FIXME: check this function.  */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	/* Disable USB ports in S3 by default */
+	gnvs->s3u0 = 0;
+	gnvs->s3u1 = 0;
+
+	/* Disable USB ports in S5 by default */
+	gnvs->s5u0 = 0;
+	gnvs->s5u1 = 0;
+
+	// the lid is open by default.
+	gnvs->lids = 1;
+
+	gnvs->tcrt = 100;
+	gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/supermicro/x9scl-f/board_info.txt b/src/mainboard/supermicro/x9scl-f/board_info.txt
new file mode 100644
index 0000000..a14680e
--- /dev/null
+++ b/src/mainboard/supermicro/x9scl-f/board_info.txt
@@ -0,0 +1,7 @@
+Category: server
+Board URL:
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2011
diff --git a/src/mainboard/supermicro/x9scl-f/devicetree.cb b/src/mainboard/supermicro/x9scl-f/devicetree.cb
new file mode 100644
index 0000000..d12f2e6f88
--- /dev/null
+++ b/src/mainboard/supermicro/x9scl-f/devicetree.cb
@@ -0,0 +1,107 @@
+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
+	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+	register "gfx.link_frequency_270_mhz" = "0"
+	register "gfx.ndid" = "3"
+	register "gfx.use_spread_spectrum_clock" = "0"
+	register "gpu_cpu_backlight" = "0x00000000"
+	register "gpu_dp_b_hotplug" = "0"
+	register "gpu_dp_c_hotplug" = "0"
+	register "gpu_dp_d_hotplug" = "0"
+	register "gpu_panel_port_select" = "0"
+	register "gpu_panel_power_backlight_off_delay" = "0"
+	register "gpu_panel_power_backlight_on_delay" = "0"
+	register "gpu_panel_power_cycle_delay" = "0"
+	register "gpu_panel_power_down_delay" = "0"
+	register "gpu_panel_power_up_delay" = "0"
+	register "gpu_pch_backlight" = "0x00000000"
+	device cpu_cluster 0x0 on
+		chip cpu/intel/model_206ax # FIXME: check all registers
+			register "c1_acpower" = "1"
+			register "c1_battery" = "1"
+			register "c2_acpower" = "3"
+			register "c2_battery" = "3"
+			register "c3_acpower" = "5"
+			register "c3_battery" = "5"
+			device lapic 0x0 on
+			end
+			device lapic 0xacac off
+			end
+		end
+	end
+	device domain 0x0 on
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "c2_latency" = "0x0065"
+			register "docking_supported" = "0"
+			register "gen1_dec" = "0x00fc0a01"
+			register "gen2_dec" = "0x00fc1641"
+			register "gen3_dec" = "0x00040ca1"
+			register "gen4_dec" = "0x001c03e1"
+			register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+			register "pcie_port_coalesce" = "1"
+			register "sata_interface_speed_support" = "0x3"
+			register "sata_port_map" = "0x3f"
+			register "spi_lvscc" = "0x0"
+			register "spi_uvscc" = "0x0"
+			device pci 16.0 off # Management Engine Interface 1
+			end
+			device pci 16.1 off # Management Engine Interface 2
+			end
+			device pci 16.2 off # Management Engine IDE-R
+			end
+			device pci 16.3 off # Management Engine KT
+			end
+			device pci 19.0 off # Intel Gigabit Ethernet
+			end
+			device pci 1a.0 on # USB2 EHCI #2
+				subsystemid 0x15d9 0x0624
+			end
+			device pci 1b.0 off # High Definition Audio
+			end
+			device pci 1c.0 on # PCIe Port #1
+				subsystemid 0x15d9 0x0624
+			end
+			device pci 1c.1 off # PCIe Port #2
+			end
+			device pci 1c.2 off # PCIe Port #3
+			end
+			device pci 1c.3 off # PCIe Port #4
+			end
+			device pci 1c.4 on # PCIe Port #5
+				subsystemid 0x15d9 0x0624
+			end
+			device pci 1c.5 off # PCIe Port #6
+			end
+			device pci 1c.6 on # PCIe Port #7
+				subsystemid 0x15d9 0x0624
+			end
+			device pci 1c.7 off # PCIe Port #8
+			end
+			device pci 1d.0 on # USB2 EHCI #1
+				subsystemid 0x15d9 0x0624
+			end
+			device pci 1e.0 on # PCI bridge
+				subsystemid 0x15d9 0x0624
+			end
+			device pci 1f.0 on # LPC bridge PCI-LPC bridge
+				subsystemid 0x15d9 0x0624
+			end
+			device pci 1f.2 on # SATA Controller 1
+				subsystemid 0x15d9 0x0624
+			end
+			device pci 1f.3 on # SMBus
+				subsystemid 0x15d9 0x0624
+			end
+			device pci 1f.5 off # SATA Controller 2
+			end
+			device pci 1f.6 off # Thermal
+			end
+		end
+		device pci 00.0 on # Host bridge Host bridge
+			subsystemid 0x15d9 0x0624
+		end
+		device pci 01.0 off # PCIe Bridge for discrete graphics
+		end
+		device pci 02.0 off # Internal graphics
+		end
+	end
+end
diff --git a/src/mainboard/supermicro/x9scl-f/dsdt.asl b/src/mainboard/supermicro/x9scl-f/dsdt.asl
new file mode 100644
index 0000000..1f86a1d
--- /dev/null
+++ b/src/mainboard/supermicro/x9scl-f/dsdt.asl
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Hosting.de GmbH
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE _SB.PCI0.GFX0
+
+#include <arch/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI 2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018	// OEM revision
+)
+{
+	/* Some generic macros */
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/bd82x6x/acpi/platform.asl>
+	/* global NVS and variables. */
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+	#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+	Device (_SB.PCI0)
+	{
+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/supermicro/x9scl-f/gpio.c b/src/mainboard/supermicro/x9scl-f/gpio.c
new file mode 100644
index 0000000..8567313
--- /dev/null
+++ b/src/mainboard/supermicro/x9scl-f/gpio.c
@@ -0,0 +1,198 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2019 Hosting.de GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_NATIVE,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_NATIVE,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_OUTPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio11 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_OUTPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio7 = GPIO_LEVEL_HIGH,
+	.gpio11 = GPIO_LEVEL_HIGH,
+	.gpio21 = GPIO_LEVEL_HIGH,
+	.gpio24 = GPIO_LEVEL_HIGH,
+	.gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio1 = GPIO_INVERT,
+	.gpio6 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_NATIVE,
+	.gpio36 = GPIO_MODE_NATIVE,
+	.gpio37 = GPIO_MODE_NATIVE,
+	.gpio38 = GPIO_MODE_NATIVE,
+	.gpio39 = GPIO_MODE_NATIVE,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_NATIVE,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NATIVE,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_NATIVE,
+	.gpio71 = GPIO_MODE_NATIVE,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/supermicro/x9scl-f/hda_verb.c b/src/mainboard/supermicro/x9scl-f/hda_verb.c
new file mode 100644
index 0000000..a5b6e19
--- /dev/null
+++ b/src/mainboard/supermicro/x9scl-f/hda_verb.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Tristan Corrick tristan@corrick.kiwi
+ * Copyright (C) 2019 Hosting.de GmbH
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {};
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/supermicro/x9scl-f/mainboard.c b/src/mainboard/supermicro/x9scl-f/mainboard.c
new file mode 100644
index 0000000..7992796
--- /dev/null
+++ b/src/mainboard/supermicro/x9scl-f/mainboard.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Hosting.de GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_enable(struct device *dev)
+{
+	/* FIXME: fix those values*/
+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+					GMA_INT15_PANEL_FIT_DEFAULT,
+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/supermicro/x9scl-f/romstage.c b/src/mainboard/supermicro/x9scl-f/romstage.c
new file mode 100644
index 0000000..426d1c9
--- /dev/null
+++ b/src/mainboard/supermicro/x9scl-f/romstage.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2019 Hosting.de GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <device/mmio.h>
+#include <device/pci_ops.h>
+#include <device/pnp_ops.h>
+#include <console/console.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
+
+void pch_enable_lpc(void)
+{
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x370f);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+}
+
+void mainboard_rcba_config(void)
+{
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[1], 0x51, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+	read_spd(&spd[3], 0x53, id_only);
+}
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9b4bf0f3caa2533b416637ce5baf4c4aad2ad94a
Gerrit-Change-Number: 34873
Gerrit-PatchSet: 1
Gerrit-Owner: Christoph Pomaska github@aufmachen.jetzt
Gerrit-MessageType: newchange



    