Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
soc/intel/alderlake: Add GPIOs for Alder Lake SOC
List of changes:
1. This implementation add the GPIO pins, communities and group mapping. 2. Add 5 GPIO community includes 16 GPIO groups GPIO COM 0 GPP_B, GPP_T, GPP_A GPIO COM 1 GPP_S, GPP_H, GPP_D, GPP_U, GPP_VGPIO GPIO COM 2 GPD GPIO COM 4 GPP_C, GPP_F, GPP_E, GPP_HVCMOD. GPP_JTAG GPIO COM 5 GPP_R, GPP_SPI 3. Add GPIO IRQ routing. 4. Add gpio.asl for ADL GPIO community. 5. Select SOC_INTEL_COMMON_BLOCK_ACPI for accessing common acpi code like gpio_op.asl
Change-Id: I77b9dcc46aceaf530e2054c9cacd7b026ebbb96b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/acpi/gpio.asl A src/soc/intel/alderlake/gpio.c A src/soc/intel/alderlake/include/soc/gpio.h A src/soc/intel/alderlake/include/soc/gpio_defs.h A src/soc/intel/alderlake/include/soc/gpio_soc_defs.h 7 files changed, 1,025 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45571/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 33acf43..550cfa3 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -23,6 +23,7 @@ select PLATFORM_USES_FSP2_2 select SOC_INTEL_COMMON select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index a0b0e36..415da13 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -17,6 +17,10 @@ romstage-y += espi.c romstage-y += meminit.c romstage-y += reset.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c +smm-y += gpio.c CPPFLAGS_common += -I$(src)/soc/intel/alderlake CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include endif diff --git a/src/soc/intel/alderlake/acpi/gpio.asl b/src/soc/intel/alderlake/acpi/gpio.asl new file mode 100644 index 0000000..f9d7f3d --- /dev/null +++ b/src/soc/intel/alderlake/acpi/gpio.asl @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <intelblocks/gpio.h> +#include <soc/gpio_defs.h> +#include <soc/intel/common/acpi/gpio.asl> +#include <soc/intel/common/block/acpi/acpi/gpio_op.asl> +#include <soc/irq.h> +#include <soc/pcr_ids.h> + +Device (GPIO) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 0) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE + + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE + + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE + + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + BAS5 = ^^PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END) + { + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPIO_COM0_START + } + /* GPIO Community 1 */ + If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END) + { + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPIO_COM1_START + } + /* GPIO Community 2 */ + If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END) + { + Local0 = PID_GPIOCOM2 + Local1 = Arg0 - GPIO_COM2_START + } + /* GPIO Community 4 */ + If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END) + { + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPIO_COM4_START + } + /* GPIO Community 05*/ + If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END) + { + Local0 = PID_GPIOCOM5 + Local1 = Arg0 - GPIO_COM5_START + } + + Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) + Return (Local2) +} + +/* + * Return PCR Port ID of GPIO Communities + * + * Arg0: GPIO Community (0-5) + */ +Method (GPID, 1, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (COMM_0) { + Local0 = PID_GPIOCOM0 + } + Case (COMM_1) { + Local0 = PID_GPIOCOM1 + } + Case (COMM_2) { + Local0 = PID_GPIOCOM2 + } + Case (COMM_4) { + Local0 = PID_GPIOCOM4 + } + Case (COMM_5) { + Local0 = PID_GPIOCOM5 + } + Default { + Return (0) + } + } + + Return (Local0) +} diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c new file mode 100644 index 0000000..2466abf --- /dev/null +++ b/src/soc/intel/alderlake/gpio.c @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/gpio.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> +#include <soc/pmc.h> + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 630094 + * Chapter number: 27 + */ + +static const struct reset_mapping rst_map[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, +}; +static const struct reset_mapping rst_map_com2[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, +}; + +/* + * The GPIO pinctrl driver for Alder Lake on Linux expects 32 GPIOs per pad + * group, regardless of whether or not there is a physical pad for each + * exposed GPIO number. + * + * This results in the OS having a sparse GPIO map, and devices that need + * to export an ACPI GPIO must use the OS expected number. + * + * Not all pins are usable as GPIO and those groups do not have a pad base. + * + * This layout matches the Linux kernel pinctrl map for ADL at: + * linux/drivers/pinctrl/intel/pinctrl-alderlake.c + */ +static const struct pad_group adl_community0_groups[] = { + INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B25, 0), /* GPP_B */ + INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 32), /* GPP_T */ + INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_A24, 64), /* GPP_A */ +}; + +static const struct pad_group adl_community1_groups[] = { + INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */ + INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128), /* GPP_H */ + INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160), /* GPP_D */ + INTEL_GPP_BASE(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK, 192), /* GPP_U */ + INTEL_GPP_BASE(GPP_S0, GPP_VGPIO_0, GPP_VGPIO_THC_1, 224), /* GPP_VGPIO */ +}; + +/* This community is not visible to the OS */ +static const struct pad_group adl_community2_groups[] = { + INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */ +}; + +static const struct pad_group adl_community4_groups[] = { + INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */ + INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288), /* GPP_F */ + INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB), /* GPP_HVCMOS */ + INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320), /* GPP_E */ + INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE), /* GPP_JTAG */ +}; + +static const struct pad_group adl_community5_groups[] = { + INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352), /* GPP_R */ + INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK), /* GPP_SPI */ +}; + +static const struct pad_community adl_communities[] = { + [COMM_0] = { /* GPP B, T, A */ + .port = PID_GPIOCOM0, + .first_pad = GPP_B0, + .last_pad = GPP_A24, + .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_BTA", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = adl_community0_groups, + .num_groups = ARRAY_SIZE(adl_community0_groups), + }, + [COMM_1] = { /* GPP S, D, H, U, VGPIO */ + .port = PID_GPIOCOM1, + .first_pad = GPP_S0, + .last_pad = GPP_VGPIO_THC_1, + .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_SDHU", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = adl_community1_groups, + .num_groups = ARRAY_SIZE(adl_community1_groups), + }, + [COMM_2] = { /* GPD */ + .port = PID_GPIOCOM2, + .first_pad = GPD0, + .last_pad = GPD_DRAM_RESETB, + .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPD", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map_com2, + .num_reset_vals = ARRAY_SIZE(rst_map_com2), + .groups = adl_community2_groups, + .num_groups = ARRAY_SIZE(adl_community2_groups), + }, + [COMM_4] = { /* GPP F, C, HVCOS, E, JTAG */ + .port = PID_GPIOCOM4, + .first_pad = GPP_C0, + .last_pad = GPP_DBG_PMODE, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_FCE", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = adl_community4_groups, + .num_groups = ARRAY_SIZE(adl_community4_groups), + }, + [COMM_5] = { /* GPP R, SPI */ + .port = PID_GPIOCOM5, + .first_pad = GPP_R0, + .last_pad = GPP_CLK_LOOPBK, + .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_CPU_VBPIO", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = adl_community5_groups, + .num_groups = ARRAY_SIZE(adl_community5_groups), + } +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(adl_communities); + return adl_communities; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + static const struct pmc_to_gpio_route routes[] = { + { PMC_GPP_B, GPP_B }, + { PMC_GPP_T, GPP_T }, + { PMC_GPP_A, GPP_A }, + { PMC_GPP_R, GPP_R }, + { PMC_GPD, GPD }, + { PMC_GPP_S, GPP_S }, + { PMC_GPP_H, GPP_H }, + { PMC_GPP_D, GPP_D }, + { PMC_GPP_U, GPP_U }, + { PMC_GPP_F, GPP_F }, + { PMC_GPP_C, GPP_C }, + { PMC_GPP_E, GPP_E }, + }; + *num = ARRAY_SIZE(routes); + return routes; +} diff --git a/src/soc/intel/alderlake/include/soc/gpio.h b/src/soc/intel/alderlake/include/soc/gpio.h new file mode 100644 index 0000000..eec698a --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_GPIO_H_ +#define _SOC_ALDERLAKE_GPIO_H_ + +#include <soc/gpio_defs.h> +#include <intelblocks/gpio.h> + +#define CROS_GPIO_NAME "INTC1055" +#define CROS_GPIO_DEVICE_NAME "INTC1055:00" + +#endif diff --git a/src/soc/intel/alderlake/include/soc/gpio_defs.h b/src/soc/intel/alderlake/include/soc/gpio_defs.h new file mode 100644 index 0000000..8d86473 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/gpio_defs.h @@ -0,0 +1,300 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_GPIO_DEFS_H_ +#define _SOC_ALDERLAKE_GPIO_DEFS_H_ + +#ifndef __ACPI__ +#include <stddef.h> +#endif +#include <soc/gpio_soc_defs.h> + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group B */ +#define GPP_B0_IRQ 0x18 +#define GPP_B1_IRQ 0x19 +#define GPP_B2_IRQ 0x1A +#define GPP_B3_IRQ 0x1B +#define GPP_B4_IRQ 0x1C +#define GPP_B5_IRQ 0x1D +#define GPP_B6_IRQ 0x1E +#define GPP_B7_IRQ 0x1F +#define GPP_B8_IRQ 0x20 +#define GPP_B9_IRQ 0x21 +#define GPP_B10_IRQ 0x22 +#define GPP_B11_IRQ 0x23 +#define GPP_B12_IRQ 0x24 +#define GPP_B13_IRQ 0x25 +#define GPP_B14_IRQ 0x26 +#define GPP_B15_IRQ 0x27 +#define GPP_B16_IRQ 0x28 +#define GPP_B17_IRQ 0x29 +#define GPP_B18_IRQ 0x2A +#define GPP_B19_IRQ 0x2B +#define GPP_B20_IRQ 0x2C +#define GPP_B21_IRQ 0x2D +#define GPP_B22_IRQ 0x2E +#define GPP_B23_IRQ 0x2F + +/* Group T */ +#define GPP_T0_IRQ 0x30 +#define GPP_T1_IRQ 0x31 +#define GPP_T2_IRQ 0x32 +#define GPP_T3_IRQ 0x33 +#define GPP_T4_IRQ 0x34 +#define GPP_T5_IRQ 0x35 +#define GPP_T6_IRQ 0x36 +#define GPP_T7_IRQ 0x37 +#define GPP_T8_IRQ 0x38 +#define GPP_T9_IRQ 0x39 +#define GPP_T10_IRQ 0x3A +#define GPP_T11IRQ 0x3B +#define GPP_T12_IRQ 0x3C +#define GPP_T13_IRQ 0x3D +#define GPP_T14_IRQ 0x3E +#define GPP_T15_IRQ 0x3F + +/* Group A */ +#define GPP_A0_IRQ 0x40 +#define GPP_A1_IRQ 0x41 +#define GPP_A2_IRQ 0x42 +#define GPP_A3_IRQ 0x43 +#define GPP_A4_IRQ 0x44 +#define GPP_A5_IRQ 0x45 +#define GPP_A6_IRQ 0x46 +#define GPP_A7_IRQ 0x47 +#define GPP_A8_IRQ 0x48 +#define GPP_A9_IRQ 0x49 +#define GPP_A10_IRQ 0x4A +#define GPP_A11_IRQ 0x4B +#define GPP_A12_IRQ 0x4C +#define GPP_A13_IRQ 0x4D +#define GPP_A14_IRQ 0x4E +#define GPP_A15_IRQ 0x4F +#define GPP_A16_IRQ 0x50 +#define GPP_A17_IRQ 0x51 +#define GPP_A18_IRQ 0x52 +#define GPP_A19_IRQ 0x53 +#define GPP_A20_IRQ 0x54 +#define GPP_A21_IRQ 0x55 +#define GPP_A22_IRQ 0x56 +#define GPP_A23_IRQ 0x57 + +/* Group R */ +#define GPP_R0_IRQ 0x58 +#define GPP_R1_IRQ 0x59 +#define GPP_R2_IRQ 0x5A +#define GPP_R3_IRQ 0x5B +#define GPP_R4_IRQ 0x5C +#define GPP_R5_IRQ 0x5D +#define GPP_R6_IRQ 0x5E +#define GPP_R7_IRQ 0x5F + +/* Group D */ +#define GPD0_IRQ 0x60 +#define GPD1_IRQ 0x61 +#define GPD2_IRQ 0x62 +#define GPD3_IRQ 0x63 +#define GPD4_IRQ 0x64 +#define GPD5_IRQ 0x65 +#define GPD6_IRQ 0x66 +#define GPD7_IRQ 0x67 +#define GPD8_IRQ 0x68 +#define GPD9_IRQ 0x69 +#define GPD10_IRQ 0x6A +#define GPD11_IRQ 0x6B + +/* Group S */ +#define GPP_S0_IRQ 0x6C +#define GPP_S1_IRQ 0x6D +#define GPP_S2_IRQ 0x6E +#define GPP_S3_IRQ 0x6F +#define GPP_S4_IRQ 0x70 +#define GPP_S5_IRQ 0x71 +#define GPP_S6_IRQ 0x72 +#define GPP_S7_IRQ 0x73 + +/* Group H */ +#define GPP_H0_IRQ 0x74 +#define GPP_H1_IRQ 0x75 +#define GPP_H2_IRQ 0x76 +#define GPP_H3_IRQ 0x77 +#define GPP_H4_IRQ 0x18 +#define GPP_H5_IRQ 0x19 +#define GPP_H6_IRQ 0x1A +#define GPP_H7_IRQ 0x1B +#define GPP_H8_IRQ 0x1C +#define GPP_H9_IRQ 0x1D +#define GPP_H10_IRQ 0x1E +#define GPP_H11_IRQ 0x1F +#define GPP_H12_IRQ 0x20 +#define GPP_H13_IRQ 0x21 +#define GPP_H14_IRQ 0x22 +#define GPP_H15_IRQ 0x23 +#define GPP_H16_IRQ 0x24 +#define GPP_H17_IRQ 0x25 +#define GPP_H18_IRQ 0x26 +#define GPP_H19_IRQ 0x27 +#define GPP_H20_IRQ 0x28 +#define GPP_H21_IRQ 0x29 +#define GPP_H22_IRQ 0x2A +#define GPP_H23_IRQ 0x2B + +/* Group D */ +#define GPP_D0_IRQ 0x2C +#define GPP_D1_IRQ 0x2D +#define GPP_D2_IRQ 0x2E +#define GPP_D3_IRQ 0x2F +#define GPP_D4_IRQ 0x30 +#define GPP_D5_IRQ 0x31 +#define GPP_D6_IRQ 0x32 +#define GPP_D7_IRQ 0x33 +#define GPP_D8_IRQ 0x34 +#define GPP_D9_IRQ 0x35 +#define GPP_D10_IRQ 0x36 +#define GPP_D11_IRQ 0x37 +#define GPP_D12_IRQ 0x38 +#define GPP_D13_IRQ 0x39 +#define GPP_D14_IRQ 0x3A +#define GPP_D15_IRQ 0x3B +#define GPP_D16_IRQ 0x3C +#define GPP_D17_IRQ 0x3D +#define GPP_D18_IRQ 0x3E +#define GPP_D19_IRQ 0x3F + +/* Group U */ +#define GPP_U0_IRQ 0x40 +#define GPP_U1IRQ 0x41 +#define GPP_U2_IRQ 0x42 +#define GPP_U3_IRQ 0x43 +#define GPP_U4_IRQ 0x44 +#define GPP_U5_IRQ 0x45 +#define GPP_U6_IRQ 0x46 +#define GPP_U7_IRQ 0x47 +#define GPP_U8_IRQ 0x48 +#define GPP_U9_IRQ 0x49 +#define GPP_U10_IRQ 0x4A +#define GPP_U11_IRQ 0x4B +#define GPP_U12_IRQ 0x4C +#define GPP_U13_IRQ 0x4D +#define GPP_U14_IRQ 0x4E +#define GPP_U15_IRQ 0x4F +#define GPP_U16_IRQ 0x50 +#define GPP_U17_IRQ 0x51 +#define GPP_U18_IRQ 0x52 +#define GPP_U19_IRQ 0x53 + +/* Group VGPIO */ +#define GPP_VGPIO4_IRQ 0x54 +#define GPP_VGPIO_THC_0_IRQ 0x3d +#define GPP_VGPIO_THC_1_IRQ 0x3e + +/* Group F */ +#define GPP_F0_IRQ 0x56 +#define GPP_F1_IRQ 0x57 +#define GPP_F2_IRQ 0x58 +#define GPP_F3_IRQ 0x59 +#define GPP_F4_IRQ 0x5A +#define GPP_F5_IRQ 0x5B +#define GPP_F6_IRQ 0x5C +#define GPP_F7_IRQ 0x5D +#define GPP_F8_IRQ 0x5E +#define GPP_F9_IRQ 0x5F +#define GPP_F10_IRQ 0x60 +#define GPP_F11_IRQ 0x61 +#define GPP_F12_IRQ 0x62 +#define GPP_F13_IRQ 0x63 +#define GPP_F14_IRQ 0x64 +#define GPP_F15_IRQ 0x65 +#define GPP_F16_IRQ 0x66 +#define GPP_F17_IRQ 0x67 +#define GPP_F18_IRQ 0x68 +#define GPP_F19_IRQ 0x69 +#define GPP_F20_IRQ 0x6A +#define GPP_F21_IRQ 0x6B +#define GPP_F22_IRQ 0x6C +#define GPP_F23_IRQ 0x6D + +/* Group C */ +#define GPP_C0_iIRQ 0x6E +#define GPP_C1_IRQ 0x6F +#define GPP_C2_IRQ 0x70 +#define GPP_C3_IRQ 0x71 +#define GPP_C4_IRQ 0x72 +#define GPP_C5_IRQ 0x73 +#define GPP_C6_IRQ 0x74 +#define GPP_C7_IRQ 0x75 +#define GPP_C8_IRQ 0x76 +#define GPP_C9_IRQ 0x77 +#define GPP_C10_IRQ 0x18 +#define GPP_C11_IRQ 0x19 +#define GPP_C12_IRQ 0x1A +#define GPP_C13_IRQ 0x1B +#define GPP_C14_IRQ 0x1C +#define GPP_C15_IRQ 0x1D +#define GPP_C16_IRQ 0x1E +#define GPP_C17_IRQ 0x1F +#define GPP_C18_IRQ 0x20 +#define GPP_C19_IRQ 0x21 +#define GPP_C20_IRQ 0x22 +#define GPP_C21_IRQ 0x23 +#define GPP_C22_IRQ 0x24 +#define GPP_C23_IRQ 0x25 + +/* Group E */ +#define GPP_E0_IRQ 0x26 +#define GPP_E1_IRQ 0x27 +#define GPP_E2_IRQ 0x28 +#define GPP_E3_IRQ 0x29 +#define GPP_E4_IRQ 0x30 +#define GPP_E5_IRQ 0x31 +#define GPP_E6_IRQ 0x32 +#define GPP_E7_IRQ 0x33 +#define GPP_E8_IRQ 0x34 +#define GPP_E9_IRQ 0x35 +#define GPP_E10_IRQ 0x36 +#define GPP_E11_IRQ 0x37 +#define GPP_E12_IRQ 0x38 +#define GPP_E13_IRQ 0x39 +#define GPP_E14_IRQ 0x3A +#define GPP_E15_IRQ 0x3B +#define GPP_E16_IRQ 0x3C +#define GPP_E17_IRQ 0x3D +#define GPP_E18_IRQ 0x3E +#define GPP_E19_IRQ 0x3F +#define GPP_E20_IRQ 0x40 +#define GPP_E21_IRQ 0x41 +#define GPP_E22_IRQ 0x42 +#define GPP_E23_IRQ 0x43 + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x110 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1A0 +#define PAD_CFG_BASE 0x700 + +#endif diff --git a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h new file mode 100644 index 0000000..fb76265 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h @@ -0,0 +1,385 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _SOC_ALDERLAKE_GPIO_SOC_DEFS_H_ +#define _SOC_ALDERLAKE_GPIO_SOC_DEFS_H_ + +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ +#define GPP_B 0x0 +#define GPP_T 0x1 +#define GPP_A 0x2 +#define GPP_R 0x3 +#define GPD 0x4 +#define GPP_S 0x5 +#define GPP_H 0x6 +#define GPP_D 0x7 +#define GPP_U 0x8 +#define GPP_F 0xA +#define GPP_C 0xB +#define GPP_E 0xC + +#define GPIO_MAX_NUM_PER_GROUP 27 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +/* GPIO community 3 is not exposed to be used and hence is skipped. */ +#define COMM_4 3 +#define COMM_5 4 +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ +/* Group B */ +#define GPP_B0 0 +#define GPP_B1 1 +#define GPP_B2 2 +#define GPP_B3 3 +#define GPP_B4 4 +#define GPP_B5 5 +#define GPP_B6 6 +#define GPP_B7 7 +#define GPP_B8 8 +#define GPP_B9 9 +#define GPP_B10 10 +#define GPP_B11 11 +#define GPP_B12 12 +#define GPP_B13 13 +#define GPP_B14 14 +#define GPP_B15 15 +#define GPP_B16 16 +#define GPP_B17 17 +#define GPP_B18 18 +#define GPP_B19 19 +#define GPP_B20 20 +#define GPP_B21 21 +#define GPP_B22 22 +#define GPP_B23 23 +#define GPP_B24 24 /* GSPI0_CLK_LOOPBK */ +#define GPP_B25 25 /* GSPI1_CLK_LOOPBK */ + +/* Group T */ +#define GPP_T0 26 +#define GPP_T1 27 +#define GPP_T2 28 +#define GPP_T3 29 +#define GPP_T4 30 +#define GPP_T5 31 +#define GPP_T6 32 +#define GPP_T7 33 +#define GPP_T8 34 +#define GPP_T9 35 +#define GPP_T10 36 +#define GPP_T11 37 +#define GPP_T12 38 +#define GPP_T13 39 +#define GPP_T14 40 +#define GPP_T15 41 + +/* Group A */ +#define GPP_A0 42 +#define GPP_A1 43 +#define GPP_A2 44 +#define GPP_A3 45 +#define GPP_A4 46 +#define GPP_A5 47 +#define GPP_A6 48 +#define GPP_A7 49 +#define GPP_A8 50 +#define GPP_A9 51 +#define GPP_A10 52 +#define GPP_A11 53 +#define GPP_A12 54 +#define GPP_A13 55 +#define GPP_A14 56 +#define GPP_A15 57 +#define GPP_A16 58 +#define GPP_A17 59 +#define GPP_A18 60 +#define GPP_A19 61 +#define GPP_A20 62 +#define GPP_A21 63 +#define GPP_A22 64 +#define GPP_A23 65 +#define GPP_A24 66 /* ESPI_CLK_LOOPBK */ + +#define GPIO_COM0_START GPP_B0 +#define GPIO_COM0_END GPP_A24 +#define NUM_GPIO_COM0_PADS (GPP_A24 - GPP_B0 + 1) + +/* Group S */ +#define GPP_S0 67 +#define GPP_S1 68 +#define GPP_S2 69 +#define GPP_S3 70 +#define GPP_S4 71 +#define GPP_S5 72 +#define GPP_S6 73 +#define GPP_S7 74 + +/* Group H */ +#define GPP_H0 75 +#define GPP_H1 76 +#define GPP_H2 77 +#define GPP_H3 78 +#define GPP_H4 79 +#define GPP_H5 80 +#define GPP_H6 81 +#define GPP_H7 82 +#define GPP_H8 83 +#define GPP_H9 84 +#define GPP_H10 85 +#define GPP_H11 86 +#define GPP_H12 87 +#define GPP_H13 88 +#define GPP_H14 89 +#define GPP_H15 90 +#define GPP_H16 91 +#define GPP_H17 92 +#define GPP_H18 93 +#define GPP_H19 94 +#define GPP_H20 95 +#define GPP_H21 96 +#define GPP_H22 97 +#define GPP_H23 98 + +/* Group D */ +#define GPP_D0 99 +#define GPP_D1 100 +#define GPP_D2 101 +#define GPP_D3 102 +#define GPP_D4 103 +#define GPP_D5 104 +#define GPP_D6 105 +#define GPP_D7 106 +#define GPP_D8 107 +#define GPP_D9 108 +#define GPP_D10 109 +#define GPP_D11 110 +#define GPP_D12 111 +#define GPP_D13 112 +#define GPP_D14 113 +#define GPP_D15 114 +#define GPP_D16 115 +#define GPP_D17 116 +#define GPP_D18 117 +#define GPP_D19 118 +#define GPP_GSPI2_CLK_LOOPBK 119 + +/* Group U */ +#define GPP_U0 120 +#define GPP_U1 121 +#define GPP_U2 122 +#define GPP_U3 123 +#define GPP_U4 124 +#define GPP_U5 125 +#define GPP_U6 126 +#define GPP_U7 127 +#define GPP_U8 128 +#define GPP_U9 129 +#define GPP_U10 130 +#define GPP_U11 131 +#define GPP_U12 132 +#define GPP_U13 133 +#define GPP_U14 134 +#define GPP_U15 135 +#define GPP_U16 136 +#define GPP_U17 137 +#define GPP_U18 138 +#define GPP_U19 139 +#define GPP_GSPI3_CLK_LOOPBK 140 +#define GPP_GSPI4_CLK_LOOPBK 141 +#define GPP_GSPI5_CLK_LOOPBK 142 +#define GPP_GSPI6_CLK_LOOPBK 143 + +/* Group VGPIO */ +#define GPP_VGPIO_0 144 +#define GPP_VGPIO_4 145 +#define GPP_VGPIO_5 146 +#define GPP_VGPIO_6 147 +#define GPP_VGPIO_7 148 +#define GPP_VGPIO_8 149 +#define GPP_VGPIO_9 150 +#define GPP_VGPIO_10 151 +#define GPP_VGPIO_11 152 +#define GPP_VGPIO_12 153 +#define GPP_VGPIO_13 154 +#define GPP_VGPIO_18 155 +#define GPP_VGPIO_19 156 +#define GPP_VGPIO_20 157 +#define GPP_VGPIO_21 158 +#define GPP_VGPIO_22 159 +#define GPP_VGPIO_23 160 +#define GPP_VGPIO_24 161 +#define GPP_VGPIO_25 162 +#define GPP_VGPIO_30 163 +#define GPP_VGPIO_31 164 +#define GPP_VGPIO_32 165 +#define GPP_VGPIO_33 166 +#define GPP_VGPIO_34 167 +#define GPP_VGPIO_35 168 +#define GPP_VGPIO_36 169 +#define GPP_VGPIO_37 170 +#define GPP_VGPIO_THC_0 171 +#define GPP_VGPIO_THC_1 172 + +#define GPIO_COM1_START GPP_S0 +#define GPIO_COM1_END GPP_VGPIO_THC_1 +#define NUM_GPIO_COM1_PADS (GPP_VGPIO_THC_1 - GPP_S0 + 1) + +/* Group GPD */ +#define GPD0 173 +#define GPD1 174 +#define GPD2 175 +#define GPD3 176 +#define GPD4 177 +#define GPD5 178 +#define GPD6 179 +#define GPD7 180 +#define GPD8 181 +#define GPD9 182 +#define GPD10 183 +#define GPD11 184 +#define GPD_INPUT3VSEL 185 +#define GPD_SLP_LANB 186 +#define GPD__SLP_SUSB 187 +#define GPD_WAKEB 188 +#define GPD_DRAM_RESETB 189 + +#define GPIO_COM2_START GPD0 +#define GPIO_COM2_END GPD_DRAM_RESETB +#define NUM_GPIO_COM2_PADS (GPD_DRAM_RESETB - GPD0 + 1) + +/* Group C */ +#define GPP_C0 190 +#define GPP_C1 191 +#define GPP_C2 192 +#define GPP_C3 193 +#define GPP_C4 194 +#define GPP_C5 195 +#define GPP_C6 196 +#define GPP_C7 197 +#define GPP_C8 198 +#define GPP_C9 199 +#define GPP_C10 200 +#define GPP_C11 201 +#define GPP_C12 202 +#define GPP_C13 203 +#define GPP_C14 204 +#define GPP_C15 205 +#define GPP_C16 206 +#define GPP_C17 207 +#define GPP_C18 208 +#define GPP_C19 209 +#define GPP_C20 210 +#define GPP_C21 211 +#define GPP_C22 212 +#define GPP_C23 213 + +/* Group F */ +#define GPP_F0 214 +#define GPP_F1 215 +#define GPP_F2 216 +#define GPP_F3 217 +#define GPP_F4 218 +#define GPP_F5 219 +#define GPP_F6 220 +#define GPP_F7 221 +#define GPP_F8 222 +#define GPP_F9 223 +#define GPP_F10 224 +#define GPP_F11 225 +#define GPP_F12 226 +#define GPP_F13 227 +#define GPP_F14 228 +#define GPP_F15 229 +#define GPP_F16 230 +#define GPP_F17 231 +#define GPP_F18 232 +#define GPP_F19 233 +#define GPP_F20 234 +#define GPP_F21 235 +#define GPP_F22 236 +#define GPP_F23 237 +#define GPP_F_CLK_LOOPBK 238 + +/* Group HVCMOS */ +#define GPP_L_BKLTEN 239 +#define GPP_L_BKLTCTL 240 +#define GPP_L_VDDEN 241 +#define GPP_SYS_PWROK 242 +#define GPP_SYS_RESETB 243 +#define GPP_MLK_RSTB 244 + +/* Group E */ +#define GPP_E0 245 +#define GPP_E1 246 +#define GPP_E2 247 +#define GPP_E3 248 +#define GPP_E4 249 +#define GPP_E5 250 +#define GPP_E6 251 +#define GPP_E7 252 +#define GPP_E8 253 +#define GPP_E9 254 +#define GPP_E10 255 +#define GPP_E11 256 +#define GPP_E12 257 +#define GPP_E13 258 +#define GPP_E14 259 +#define GPP_E15 260 +#define GPP_E16 261 +#define GPP_E17 262 +#define GPP_E18 263 +#define GPP_E19 264 +#define GPP_E20 265 +#define GPP_E21 266 +#define GPP_E22 267 +#define GPP_E23 268 +#define GPP_E_CLK_LOOPBK 269 + +/* Group JTAG */ +#define GPP_JTAG_TDO 270 +#define GPP_JTAG_X 271 +#define GPP_JTAG_PRDYB 272 +#define GPP_JTAG_PREQB 273 +#define GPP_CPU_TRSTB 274 +#define GPP_JTAG_TDI 275 +#define GPP_JTAG_TMS 276 +#define GPP_JTAG_TCK 277 +#define GPP_DBG_PMODE 278 + +#define GPIO_COM4_START GPP_C0 +#define GPIO_COM4_END GPP_DBG_PMODE +#define NUM_GPIO_COM4_PADS (GPP_DBG_PMODE - GPP_C0 + 1) + +/* Group R */ +#define GPP_R0 279 +#define GPP_R1 280 +#define GPP_R2 281 +#define GPP_R3 282 +#define GPP_R4 283 +#define GPP_R5 284 +#define GPP_R6 285 +#define GPP_R7 286 + +/* Group SPI */ +#define GPP_SPI_IO_2 287 +#define GPP_SPI_IO_3 288 +#define GPP_SPI_MOSI_IO_0 289 +#define GPP_SPI_MOSI_IO_1 290 +#define GPP_SPI_TPM_CSB 291 +#define GPP_SPI_FLASH_0_CSB 292 +#define GPP_SPI_FLASH_1_CSB 293 +#define GPP_SPI_CLK 294 +#define GPP_CLK_LOOPBK 295 + +#define GPIO_COM5_START GPP_R0 +#define GPIO_COM5_END GPP_CLK_LOOPBK +#define NUM_GPIO_COM5_PADS (GPP_CLK_LOOPBK - GPP_R0 + 1) + +#define TOTAL_GPIO_COMM (COMM_5 + 1) +#define TOTAL_PADS (GPIO_COM5_END + 1) + +#endif
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 1:
(6 comments)
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/Kco... File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/Kco... PS1, Line 26: SOC_INTEL_COMMON_BLOCK_ACPI Should go in as a separate change?
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/Mak... File src/soc/intel/alderlake/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/Mak... PS1, Line 20: bootblock-y += gpio.c : romstage-y += gpio.c : ramstage-y += gpio.c : smm-y += gpio.c I think these files are typically arranged in groups based on stages.
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/acp... File src/soc/intel/alderlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/acp... PS1, Line 9: GPIO Not for this change, but I would really like to see this getting generated using SSDT. I think we can take advantage of all the GPIO community tables we add in gpio.c.
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/acp... PS1, Line 11: CROS_GPIO_NAME Have you verified that this matches the Linux kernel expectations? I know JSL and TGL used very different ways of handling the different communities.
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/gpi... File src/soc/intel/alderlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/gpi... PS1, Line 27: The GPIO pinctrl driver for Alder Lake on Linux expects 32 GPIOs per pad Have you confirmed this?
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/gpi... PS1, Line 36: This layout matches the Linux kernel pinctrl map for ADL at: : * linux/drivers/pinctrl/intel/pinctrl-alderlake.c What version of Linux kernel? I did not find this file in v5.9-rc6.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/acp... File src/soc/intel/alderlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/acp... PS1, Line 11: CROS_GPIO_NAME
Have you verified that this matches the Linux kernel expectations? I know JSL and TGL used very diff […]
This name is as per GPIO chapter and linux should use the same name.
in TGL i could see https://github.com/coreboot/coreboot/blob/master/src/soc/intel/tigerlake/inc... and gpio.asl has hardcoded the same https://github.com/coreboot/coreboot/blob/master/src/soc/intel/tigerlake/acp...
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/gpi... File src/soc/intel/alderlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/gpi... PS1, Line 27: The GPIO pinctrl driver for Alder Lake on Linux expects 32 GPIOs per pad
Have you confirmed this?
we have the same practice in CNL and TGL, and don't expect to change in ADL too (what i learn from chrome os team)
https://github.com/coreboot/coreboot/blob/master/src/soc/intel/cannonlake/gp...
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/gpi... PS1, Line 36: This layout matches the Linux kernel pinctrl map for ADL at: : * linux/drivers/pinctrl/intel/pinctrl-alderlake.c
What version of Linux kernel? I did not find this file in v5.9-rc6.
this is more over a placeholder as i understood,
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/acp... File src/soc/intel/alderlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/acp... PS1, Line 11: CROS_GPIO_NAME
This name is as per GPIO chapter and linux should use the same name. […]
I just wanted to make sure that we are matching Linux kernel expectations w.r.t. exposing a single device for the GPIO controller or have a device per community. I think JSL started out with a single device per community, but switched to single device for the controller.
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/gpi... File src/soc/intel/alderlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/gpi... PS1, Line 27: The GPIO pinctrl driver for Alder Lake on Linux expects 32 GPIOs per pad
we have the same practice in CNL and TGL, and don't expect to change in ADL too (what i learn from c […]
SG. Just wanted to make sure that you have talked to the kernel team. We had different implementations early on for TGL/JSL.
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/gpi... PS1, Line 36: This layout matches the Linux kernel pinctrl map for ADL at: : * linux/drivers/pinctrl/intel/pinctrl-alderlake.c
this is more over a placeholder as i understood,
Umm.. I think it would be good to point to an actual reference. I understand that this file might not be really present at this point. I was just curious if this file is already checked into some maintainer tree or some place you could point to.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/gpi... File src/soc/intel/alderlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/gpi... PS1, Line 36: This layout matches the Linux kernel pinctrl map for ADL at: : * linux/drivers/pinctrl/intel/pinctrl-alderlake.c
Umm.. I think it would be good to point to an actual reference. […]
i know its there at some sandbox or chromium repo for sure
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/Kco... File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/Kco... PS1, Line 26: SOC_INTEL_COMMON_BLOCK_ACPI
Should go in as a separate change?
Ack
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/Mak... File src/soc/intel/alderlake/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/Mak... PS1, Line 20: bootblock-y += gpio.c : romstage-y += gpio.c : ramstage-y += gpio.c : smm-y += gpio.c
I think these files are typically arranged in groups based on stages.
Ack
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/gpi... File src/soc/intel/alderlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/45571/1/src/soc/intel/alderlake/gpi... PS1, Line 36: This layout matches the Linux kernel pinctrl map for ADL at: : * linux/drivers/pinctrl/intel/pinctrl-alderlake.c
i know its there at some sandbox or chromium repo for sure
Ack
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45571
to look at the new patch set (#2).
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
soc/intel/alderlake: Add GPIOs for Alder Lake SOC
List of changes:
1. This implementation add the GPIO pins, communities and group mapping. 2. Add 5 GPIO community includes 13 GPIO groups GPIO COM 0 GPP_B, GPP_T, GPP_A GPIO COM 1 GPP_S, GPP_H, GPP_D GPIO COM 2 GPD GPIO COM 4 GPP_C, GPP_F, GPP_E, GPP_HVCMOD GPIO COM 5 GPP_R, GPP_SPI 3. Add GPIO IRQ routing. 4. Add gpio.asl for ADL GPIO community.
Change-Id: I77b9dcc46aceaf530e2054c9cacd7b026ebbb96b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/acpi/gpio.asl A src/soc/intel/alderlake/gpio.c A src/soc/intel/alderlake/include/soc/gpio.h A src/soc/intel/alderlake/include/soc/gpio_defs.h A src/soc/intel/alderlake/include/soc/gpio_soc_defs.h 6 files changed, 927 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45571/2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 2:
(5 comments)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 189: __ one _
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 187: GPD_INPUT3VSEL 132 : #define GPD_SLP_LANB 133 : #define GPD__SLP_SUSB 134 keep them in-line with cnl, where GPD_ prefix was skipped? same for the others. This way the name matches with the pin names in schematics.
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 302: #define GPP_SPI_MOSI_IO_0 227 : #define GPP_SPI_MOSI_IO_1 22 these two names are confusing, since there can't be two MOSI. Let's use SPI0_MOSI, SPI0_MISO
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 305: PI_FLASH_0_CSB 230 : #define GPP_SPI_FLASH_1_CSB SPI_CS0_B SPI_CS1_B
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309: missing: azalia, jtag, cpu, vgpio*
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
missing: azalia, jtag, cpu, vgpio*
these are not part of SoC EDS chapter as i have added above, hence don't expect BIOS to configure.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
these are not part of SoC EDS chapter as i have added above, hence don't expect BIOS to configure.
FSP configures some of them (there are even UPDs which do nothing but set a pin to NF1...). Isn't FSP part of "BIOS"?
Curious, are they documented elsewhere except FSP source?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
FSP configures some of them (there are even UPDs which do nothing but set a pin to NF1...). […]
One more question - what's the difference to CNL, where these pins are even know to the Linux kernel? (drivers/pinctrl/intel/pinctrl-cannonlake.c)
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 2: Code-Review+1
(18 comments)
Some comments, but looks good overall.
https://review.coreboot.org/c/coreboot/+/45571/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45571/2//COMMIT_MSG@9 PS2, Line 9: List of changes: : : 1. This implementation add the GPIO pins, communities and : group mapping. : 2. Add 5 GPIO community includes 13 GPIO groups : GPIO COM 0 : GPP_B, GPP_T, GPP_A : GPIO COM 1 : GPP_S, GPP_H, GPP_D : GPIO COM 2 : GPD : GPIO COM 4 : GPP_C, GPP_F, GPP_E, GPP_HVCMOD : GPIO COM 5 : GPP_R, GPP_SPI : 3. Add GPIO IRQ routing. : 4. Add gpio.asl for ADL GPIO community. Instead of having a list of changes, I'd say the following:
Add definitions for the GPIO pins on Alder Lake LP, as well as GPIO IRQ routing information and supporting ACPI ASL.
For now, add the following 5 GPIO communities and 13 GPIO groups:
Comm. 0: GPP_B, GPP_T, GPP_A Comm. 1: GPP_S, GPP_H, GPP_D Comm. 2: GPD Comm. 4: GPP_C, GPP_F, GPP_E, GPP_HVCMOS Comm. 5: GPP_R, GPP_SPI
I assume `GPP_HVCMOD` is a typo? 😊
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/acp... File src/soc/intel/alderlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/acp... PS2, Line 89: 05 5
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... File src/soc/intel/alderlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... PS2, Line 35: * nit: trailing blank line in comment
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... PS2, Line 66: static const struct pad_community adl_communities[] = { Looks like these GPIO definitions are specific to ADL PCH-LP. Maybe we want to support PCH-S someday?
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... PS2, Line 69: GPP_B0 GPIO_COM0_START
Same for all communities
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... PS2, Line 70: GPP_ESPI_CLK_LOOPBK GPIO_COM0_END
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 14: (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) DIV_ROUND_UP((n), GPIO_MAX_NUM_PER_GROUP)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 70: GPP_T11IRQ missing a _
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
PS2: If we don't need to use these definitions in ACPI, we could use enums instead.
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 13: #define GPP_R 0x3 The SPI group is mentioned in the commit message, but it's not here? Also, isn't SPI = 0x4? If so, the other GPIO groups would be off by one.
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 18: GPP_U hmm, I don't see any other definitions for Group U?
In any case, Group U consists of 24 pins: - GPP_U0 .. GPP_U19 (20 pins) - GSPI{3,4,5,6}_CLK_LOOPBACK (4 pins)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 19: #define GPP_F 0xA : #define GPP_C 0xB I think these two are backwards. GPP_C = 0xb, but isn't GPP_F = 0xc?
Also, HVCMOS = 0xd seems to be missing.
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 174: nit: a single space is enough
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 187: GPD_INPUT3VSEL 132 : #define GPD_SLP_LANB 133 : #define GPD__SLP_SUSB 134
keep them in-line with cnl, where GPD_ prefix was skipped? same for the others. […]
I doubt CNL is a good example on how to do things. We had a problem with a macro named `PECI`, didn't we?
In any case, it would be nice to use a prefix to namespace these GPIO definitions. But this would need to be done on all platforms.
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 302: #define GPP_SPI_MOSI_IO_0 227 : #define GPP_SPI_MOSI_IO_1 22
these two names are confusing, since there can't be two MOSI. […]
I don't think the proposed renaming is a good idea. When in Dual or Quad I/O mode, these pins are actually IO_0 and IO_1. If anything, the whole SPI group should be renamed, but if this is the only SPI group, it doesn't matter.
In any case, looks like IO_1 should be MISO.
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 305: PI_FLASH_0_CSB 230 : #define GPP_SPI_FLASH_1_CSB
SPI_CS0_B […]
`CSx` makes it harder to differentiate the macros. Having the numbers separated eases distinction. IMHO, I'd stick to what the EDS says.
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 308: GPP_CLK_LOOPBK nit: missing the `SPI_` part: GPP_SPI_CLK_LOOPBK
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
these are not part of SoC EDS chapter as i have added above, hence don't expect BIOS to configure.
I think we would want to configure some of these GPIOs someday. But since ADL is not released yet, I don't mind if the definitions get added once it is.
Michael: I can't see Azalia in the GPIO group list, but looks like these pins exist in the CPU group. Also, I imagine the kernel doesn't have definitions for ADL GPIOs because ADL is not released yet.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 187: GPD_INPUT3VSEL 132 : #define GPD_SLP_LANB 133 : #define GPD__SLP_SUSB 134
I doubt CNL is a good example on how to do things. […]
right, we *had* a problem; it's merged...
ACK on consitency between all platforms
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 302: #define GPP_SPI_MOSI_IO_0 227 : #define GPP_SPI_MOSI_IO_1 22
I don't think the proposed renaming is a good idea. […]
The names _MOSI_ are wrong in EDS and FSP already, where those names come from. I would name the pins like they are named in PCH ds and (later) in (RVP) schematics.
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 305: PI_FLASH_0_CSB 230 : #define GPP_SPI_FLASH_1_CSB
`CSx` makes it harder to differentiate the macros. Having the numbers separated eases distinction. […]
Same as above; yes, it makes it harder to differentiate, however, I'd keep the "real" names of the pins here
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
I think we would want to configure some of these GPIOs someday. But since ADL is not released yet, I don't mind if the definitions get added once it is.
ACK
Michael: I can't see Azalia in the GPIO group list, but looks like these pins exist in the CPU group.
Depends, have a look at CNL in Linux and coreboot. HDACPU pins are in the CPU group, while AZALIA is a group on its own.
Also, I imagine the kernel doesn't have definitions for ADL GPIOs because ADL is not released yet.
Yeah, I think so, too
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 2: Code-Review+1
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... File src/soc/intel/alderlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... PS2, Line 177: GPD nit: line up with the others
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 235: : /* Group E */ : #define GPP_E0_IRQ 0x26 : #define GPP_E1_IRQ 0x27 : #define GPP_E2_IRQ 0x28 : #define GPP_E3_IRQ 0x29 : #define GPP_E4_IRQ 0x30 : #define GPP_E5_IRQ 0x31 : #define GPP_E6_IRQ 0x32 : #define GPP_E7_IRQ 0x33 : #define GPP_E8_IRQ 0x34 : #define GPP_E9_IRQ 0x35 : #define GPP_E10_IRQ 0x36 : #define GPP_E11_IRQ 0x37 : #define GPP_E12_IRQ 0x38 : #define GPP_E13_IRQ 0x39 : #define GPP_E14_IRQ 0x3A : #define GPP_E15_IRQ 0x3B : #define GPP_E16_IRQ 0x3C : #define GPP_E17_IRQ 0x3D : #define GPP_E18_IRQ 0x3E : #define GPP_E19_IRQ 0x3F : #define GPP_E20_IRQ 0x40 : #define GPP_E21_IRQ 0x41 : #define GPP_E22_IRQ 0x42 : #define GPP_E23_IRQ 0x43 can you move this between D and F?
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 23: 27 I don't see more than 24
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
I think we would want to configure some of these GPIOs someday. But since ADL is not released yet, I don't mind if the definitions get added once it is.
ACK
Michael: I can't see Azalia in the GPIO group list, but looks like these pins exist in the CPU group.
EDS doesn't provide details about GPIO COMM 3 which typically has those SoC only GPIO configuration as you have asked for. From board design side, we don't expect those GPIOs would be used for any other purpose than being SoC only use. Hence COMM 3 doesn't expose those GPIO PIN in EDS. Same goes for VGPIO, JTAG, those are reserved for SOC only use and don't expect even FSP also does those programming as well.
Any GPIO with PIN MUX feature FSP has UPD to ignore FSP to program, for example: if I2C3 doesn't have device attached on board we make the UPD disable and FSP won't program the associate GPIOs hence the same GPIO can be used a general purpose (other than being NF) for other board component usage.
Depends, have a look at CNL in Linux and coreboot. HDACPU pins are in the CPU group, while AZALIA is a group on its own.
Also, I imagine the kernel doesn't have definitions for ADL GPIOs because ADL is not released yet.
Yeah, I think so, too
GPIO definition only available in EDS chapter 27 and BIOS and kernel should have same snapshot, in past i know for chromeos, folks use to refer from coreboot code to align the kernel (from ICL exp I can say so). For ADL the pin controller driver in kernel will follow the same process and ensure the sync.
Curious, are they documented elsewhere except FSP source?
EDS is the best place, FSP can program the NF and always attached with UPD, this is the process we have ensure to avoid wrong function getting programmed or FSP overrides something what CB does
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 2:
(20 comments)
https://review.coreboot.org/c/coreboot/+/45571/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45571/2//COMMIT_MSG@9 PS2, Line 9: List of changes: : : 1. This implementation add the GPIO pins, communities and : group mapping. : 2. Add 5 GPIO community includes 13 GPIO groups : GPIO COM 0 : GPP_B, GPP_T, GPP_A : GPIO COM 1 : GPP_S, GPP_H, GPP_D : GPIO COM 2 : GPD : GPIO COM 4 : GPP_C, GPP_F, GPP_E, GPP_HVCMOD : GPIO COM 5 : GPP_R, GPP_SPI : 3. Add GPIO IRQ routing. : 4. Add gpio.asl for ADL GPIO community.
Instead of having a list of changes, I'd say the following: […]
Thanks for suggestion.
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/acp... File src/soc/intel/alderlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/acp... PS2, Line 89: 05
5
Ack
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... File src/soc/intel/alderlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... PS2, Line 35: *
nit: trailing blank line in comment
Ack
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... PS2, Line 69: GPP_B0
GPIO_COM0_START […]
Ack
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... PS2, Line 70: GPP_ESPI_CLK_LOOPBK
GPIO_COM0_END
Ack
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... PS2, Line 177: GPD
nit: line up with the others
Ack
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 14: (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
DIV_ROUND_UP((n), GPIO_MAX_NUM_PER_GROUP)
src/commonlib/bsd/include/commonlib/bsd/helpers.h:57:28: error: braced-group within expression allowed only inside a function 57 | #define DIV_ROUND_UP(x, y) ({ \ | ^ src/soc/intel/alderlake/include/soc/gpio_defs_lp.h:14:35: note: in expansion of macro 'DIV_ROUND_UP' 14 | #define NUM_GPIO_COMx_GPI_REGS(n) DIV_ROUND_UP((n), GPIO_MAX_NUM_PER_GROUP)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 70: GPP_T11IRQ
missing a _
Ack
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 235: : /* Group E */ : #define GPP_E0_IRQ 0x26 : #define GPP_E1_IRQ 0x27 : #define GPP_E2_IRQ 0x28 : #define GPP_E3_IRQ 0x29 : #define GPP_E4_IRQ 0x30 : #define GPP_E5_IRQ 0x31 : #define GPP_E6_IRQ 0x32 : #define GPP_E7_IRQ 0x33 : #define GPP_E8_IRQ 0x34 : #define GPP_E9_IRQ 0x35 : #define GPP_E10_IRQ 0x36 : #define GPP_E11_IRQ 0x37 : #define GPP_E12_IRQ 0x38 : #define GPP_E13_IRQ 0x39 : #define GPP_E14_IRQ 0x3A : #define GPP_E15_IRQ 0x3B : #define GPP_E16_IRQ 0x3C : #define GPP_E17_IRQ 0x3D : #define GPP_E18_IRQ 0x3E : #define GPP_E19_IRQ 0x3F : #define GPP_E20_IRQ 0x40 : #define GPP_E21_IRQ 0x41 : #define GPP_E22_IRQ 0x42 : #define GPP_E23_IRQ 0x43
can you move this between D and F?
Ack
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
PS2:
If we don't need to use these definitions in ACPI, we could use enums instead.
we are using in ACPI 😞
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 13: #define GPP_R 0x3
The SPI group is mentioned in the commit message, but it's not here? Also, isn't SPI = 0x4? If so, t […]
Ack
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 18: GPP_U
hmm, I don't see any other definitions for Group U? […]
Ack
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 19: #define GPP_F 0xA : #define GPP_C 0xB
I think these two are backwards. GPP_C = 0xb, but isn't GPP_F = 0xc? […]
Ack
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 23: 27
I don't see more than 24
Ack, its 26 at max due to GPP_B (0 to 25)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 174:
nit: a single space is enough
Ack
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 189: __
one _
Ack
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 187: GPD_INPUT3VSEL 132 : #define GPD_SLP_LANB 133 : #define GPD__SLP_SUSB 134
right, we *had* a problem; it's merged... […]
Right now TGL and JSL has GPD_ prefix. marking resolve, let me know if i need to remove those ?
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 302: #define GPP_SPI_MOSI_IO_0 227 : #define GPP_SPI_MOSI_IO_1 22
The names _MOSI_ are wrong in EDS and FSP already, where those names come from. […]
Added the exact name matching schematics
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 305: PI_FLASH_0_CSB 230 : #define GPP_SPI_FLASH_1_CSB
Same as above; yes, it makes it harder to differentiate, however, I'd keep the "real" names of the p […]
Added the exact name matching schematics
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 308: GPP_CLK_LOOPBK
nit: missing the `SPI_` part: GPP_SPI_CLK_LOOPBK
This PIN in not there, removed it now
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45571
to look at the new patch set (#3).
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
soc/intel/alderlake: Add GPIOs for Alder Lake SOC
Add definitions for the GPIO pins on Alder Lake LP, as well as GPIO IRQ routing information and supporting ACPI ASL.
For now, add the following 5 GPIO communities and 13 GPIO groups:
Comm. 0: GPP_B, GPP_T, GPP_A Comm. 1: GPP_S, GPP_H, GPP_D Comm. 2: GPD Comm. 4: GPP_C, GPP_F, GPP_E, GPP_HVMOS Comm. 5: GPP_R, GPP_SPI0
Change-Id: I77b9dcc46aceaf530e2054c9cacd7b026ebbb96b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/acpi/gpio.asl A src/soc/intel/alderlake/gpio.c A src/soc/intel/alderlake/include/soc/gpio.h A src/soc/intel/alderlake/include/soc/gpio_defs.h A src/soc/intel/alderlake/include/soc/gpio_soc_defs.h M src/soc/intel/alderlake/include/soc/pmc.h 7 files changed, 945 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45571/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 14: (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
src/commonlib/bsd/include/commonlib/bsd/helpers. […]
Ah, hrm. I ran into this problem too.
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45571
to look at the new patch set (#4).
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
soc/intel/alderlake: Add GPIOs for Alder Lake SOC
Add definitions for the GPIO pins on Alder Lake LP, as well as GPIO IRQ routing information and supporting ACPI ASL.
For now, add the following 5 GPIO communities and 13 GPIO groups:
Comm. 0: GPP_B, GPP_T, GPP_A Comm. 1: GPP_S, GPP_H, GPP_D Comm. 2: GPD Comm. 4: GPP_C, GPP_F, GPP_E, GPP_HVMOS Comm. 5: GPP_R, GPP_SPI0
Change-Id: I77b9dcc46aceaf530e2054c9cacd7b026ebbb96b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/acpi/gpio.asl A src/soc/intel/alderlake/gpio.c A src/soc/intel/alderlake/include/soc/gpio.h A src/soc/intel/alderlake/include/soc/gpio_defs.h A src/soc/intel/alderlake/include/soc/gpio_soc_defs.h M src/soc/intel/alderlake/include/soc/pmc.h 7 files changed, 945 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45571/4
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 4: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/45571/4/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/4/src/soc/intel/alderlake/inc... PS4, Line 310: 229 One tab too many?
https://review.coreboot.org/c/coreboot/+/45571/4/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/45571/4/src/soc/intel/alderlake/inc... PS4, Line 138: 0x9 Needs one more tab
https://review.coreboot.org/c/coreboot/+/45571/4/src/soc/intel/alderlake/inc... PS4, Line 141: 0xC Another tab here
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45571
to look at the new patch set (#5).
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
soc/intel/alderlake: Add GPIOs for Alder Lake SOC
Add definitions for the GPIO pins on Alder Lake LP, as well as GPIO IRQ routing information and supporting ACPI ASL.
For now, add the following 5 GPIO communities and 13 GPIO groups:
Comm. 0: GPP_B, GPP_T, GPP_A Comm. 1: GPP_S, GPP_H, GPP_D Comm. 2: GPD Comm. 4: GPP_C, GPP_F, GPP_E, GPP_HVMOS Comm. 5: GPP_R, GPP_SPI0
Change-Id: I77b9dcc46aceaf530e2054c9cacd7b026ebbb96b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/acpi/gpio.asl A src/soc/intel/alderlake/gpio.c A src/soc/intel/alderlake/include/soc/gpio.h A src/soc/intel/alderlake/include/soc/gpio_defs.h A src/soc/intel/alderlake/include/soc/gpio_soc_defs.h M src/soc/intel/alderlake/include/soc/pmc.h 7 files changed, 945 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45571/5
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45571/4/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/4/src/soc/intel/alderlake/inc... PS4, Line 310: 229
One tab too many?
Ack
https://review.coreboot.org/c/coreboot/+/45571/4/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/45571/4/src/soc/intel/alderlake/inc... PS4, Line 138: 0x9
Needs one more tab
Ack
https://review.coreboot.org/c/coreboot/+/45571/4/src/soc/intel/alderlake/inc... PS4, Line 141: 0xC
Another tab here
Ack
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
and don't expect even FSP also does those programming as well.
Sorry, I can't parse that. Do you mean "FSP does not program these GPIOs" (vGPIO for example?) If yes, then this is untrue - for CNL as well as ICL, TGL and probably ADL.
Any GPIO with PIN MUX feature FSP has UPD to ignore FSP to program, for example: if I2C3 doesn't have device attached on board we make the UPD disable
Well, FSP in some cases does nothing more than setting NF1, which coreboot can, too.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... File src/soc/intel/alderlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... PS2, Line 66: static const struct pad_community adl_communities[] = {
Looks like these GPIO definitions are specific to ADL PCH-LP. […]
for cannonlake, we ended up with two headers ...defs_cnp_h.h & ...defs.h. and then a CONFIG to select between them; not the prettiest though, we may be able to think of something better
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... File src/soc/intel/alderlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... PS2, Line 66: static const struct pad_community adl_communities[] = {
for cannonlake, we ended up with two headers ...defs_cnp_h.h & ...defs.h. […]
We'll see. No rush
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... File src/soc/intel/alderlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... PS2, Line 66: static const struct pad_community adl_communities[] = {
We'll see. […]
yes, i had the same plan, even my code was ready in that way but when we upstream we shall do in same way
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
and don't expect even FSP also does those programming as well.
Sorry, I can't parse that. Do you mean "FSP does not program these GPIOs" (vGPIO for example?) If yes, then this is untrue - for CNL as well as ICL, TGL and probably ADL.
if its only SOC GPIO which doesn't need to have any board configuration point like JTAG, CPU, SPI0 etc. is meant to only set to default and BIOS (coreboot or FSP) don't expect to program those. Anything we wish to program should have been documented in EDS. If you have seen other cases it might be a bug and better to follow up that.
We have also seen some cases in past platform where FSP unnecessary program new GPIO in Native mode (this is only what FSP can do) and coreboot want to use that as GPIO mode hence we have possibly guard all such NF programming GPIO inside FSP using UPD to ensure it doesn't override coreboot GPIO pad configuration.
Any GPIO with PIN MUX feature FSP has UPD to ignore FSP to program, for example: if I2C3 doesn't have device attached on board we make the UPD disable
Well, FSP in some cases does nothing more than setting NF1, which coreboot can, too.
Yes, FSP can only set GPIO to NF but my point is if board design don't like to use that GPIO in NF then FSP shouldn't do that override even, hence we have guarded all NF inside FSP using possible UPD to avoid overrides
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
and don't expect even FSP also does those programming as well. […]
It could also be that EDS is missing these GPIOs. I think it's rather usual for early revisions of documents to lack some information.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
It could also be that EDS is missing these GPIOs. […]
HI Angel, Before opening those code, i have confirmed from EDS owner that those GPIOs are not intended to program by BIOS and will use as SoC default hence EDS doesn't even bother to open those. I have some internal doc which also justify the same claim hence we are good for now.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
HI Angel, Before opening those code, i have confirmed from EDS owner that those GPIOs are not intend […]
Proving little more information here all GPIO PIN that Michael has asked like Azalia, CPU, VGPIO are part of GPIO COMM 3 which we don't expose for Linux driver and BIOS. i hope this is good to have information.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
We have also seen some cases in past platform where FSP unnecessary program new GPIO in Native mode (this is only what FSP can do)
Sorry, the latter part again is untrue. I was and I am able to change them in coreboot, just like the "normal" GPIOs. I've been experimenting with those "special" GPIOs a few days on CML.
i have confirmed from EDS owner that those GPIOs are not intended to program by BIOS
FSP indirectly claims being part of "BIOS" in multiple comments in the source. You see comments like "BIOS is expected to do xyz", at code locations doing exactly what's in the comments. Yes, that may be a weak conclusion. However, the point is it does program these GPIOs.
Yes, FSP can only set GPIO to NF but my point is if board design don't like to use that GPIO in NF then FSP shouldn't do that override even, hence we have guarded all NF inside FSP using possible UPD to avoid overrides
Yes, this is right and I fully agree. There are UPDs that make FSP configure those pads as NF1. For a (probably incomplete) list for CNL, see CB:45211.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309: I forgot this one:
Proving little more information here all GPIO PIN that Michael has asked like Azalia, CPU, VGPIO are part of GPIO COMM 3 which we don't expose for Linux driver and BIOS. i hope this is good to have information.
We may not want to expose it to Linux but Linux (OS) != coreboot (BIOS). Claiming not exposing it to BIOS sounds a bit dishonest, given the fact that they are indeed exposed to FSP which is part of BIOS.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
Sorry, the latter part again is untrue. I was and I am able to change them in coreboot, just like the "normal" GPIOs. I've been experimenting with those "special" GPIOs a few days on CML.
All GPIOs are MMIO mapped hence you can do experiment as long as you know the addresses.
FSP indirectly claims being part of "BIOS" in multiple comments in the source. You see comments like "BIOS is expected to do xyz", at code locations doing exactly what's in the comments. Yes, that may be a weak conclusion. However, the point is it does program these GPIOs.
FSP meant to do SoC GPIO programming in NF, no doubt about that but as per guideline i have received from GPIO owner, your interest point GPIOs are not going to program in FSP as well hence SOC default we are going to use.
I forgot this one:
Proving little more information here all GPIO PIN that Michael has asked like Azalia, CPU, VGPIO are part of GPIO COMM 3 which we don't expose for Linux driver and BIOS. i hope this is good to have information.
We may not want to expose it to Linux but Linux (OS) != coreboot (BIOS). Claiming not exposing it to BIOS sounds a bit dishonest, given the fact that they are indeed exposed to FSP which is part of BIOS.
So far i don't see such programming in FSP and as i said the plan is to use SoC default. Also this is what i'm suppose to upstream at this moment, i have clear legal and all other doubts based on board schematics that those GPIO we might not need to touch in coreboot as well.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
Sorry, the latter part again is untrue. […]
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5: Code-Review+1
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
Done
Not sure if you have ADL Chapter 18 GPIO section access, i don't see any public document for this, its mostly internal document, all GPIO that you have asked question "cpu, Azalia, JTAG and VGPIO" been listed under "NON-GPIO Native only IO Muxing" which is set to default NF mode at reset.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
Not sure if you have ADL Chapter 18 GPIO section access, i don't see any public document for this, i […]
I was asked to comment here, but I don't have the time to dive deep into documentation. So I'll try to point out some potential communi- cation issue: I think the biggest problem is that people still refer to this as "GPIO config". But it's much bigger today. What we do here is "pad configuration". It's not anymore about GPIOs only (which were the first pins that are configurable and to have muxes, but that was ten years ago), there are many more configurable pads today even if not used as GPIO.
I believe, coreboot has to configure all pads that need configu- ration even if it's just choosing one NF over another or just to enable the only NF instead of configuring some pull. If coreboot needs to set any FSP UPD to configure a pad, then we failed to do our job. The reason is simple: there is an incredible amount of configurable pads today and somebody needs to review their confi- guration. Reviewers are humans and humans fail from time to time. If the configuration is spread across many places, it is much more likely that errors sneak in, quality gets lower and time-to-market is longer. Currently, Intel seems to lower the coreboot quality with their "this is BIOS, this is not" policies, but I don't think they want to. It's an accident, accidents happen. It's our job now to fix that for the future and make it clear that all pad confi- guration has to happen in coreboot.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
I was asked to comment here, but I don't have the time to dive deep […]
To solve this, one option would be to have an `opt-in` FSP option for pad configuration:
- When not set, FSP does not change the state of any pads. This is what would be used in coreboot. - When set, FSP can configure pads. This is to preserve existing functionality, in case other users of FSP do pad configuration via FSP.
I think this is a relatively simple change to implement.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
To solve this, one option would be to have an `opt-in` FSP option for pad configuration: […]
Angel, please check this https://github.com/coreboot/coreboot/blob/master/src/soc/intel/tigerlake/rom...
I'm had refer about SoC default GPIO :) not sure if i have done in mistake conveying the same where FSP also don't touch those GPIOs. ideally no one program those PADs, one could argue, what happen if i want to touch from coreboot, its okay to do i believe as long as its part of EDS, which is not the case, so if like to do randomly knowing there is GPIO COMM 3 and let configure those to NF without knowing the PIN number and description is only my concern.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
Angel, please check this https://github. […]
Ah, GpioOverride must be *very* new. Subrata, is it possible to internally suggest that we get this for CNL and others, too?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
Ah, GpioOverride must be *very* new. […]
just for reference: https://github.com/coreboot/coreboot/commit/dc87025ce41f24c8c3337176c3e38f23...
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
just for reference: https://github. […]
I can file a bug for CNL FSP and share feedback with you.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
I can file a bug for CNL FSP and share feedback with you.
Great! Thank you, CML and maybe others, too, if possible, please :-)
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
Great! Thank you, CML and maybe others, too, if possible, please :-)
Sure, CML, ICL and CNL is your wish list, let me explore as well
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/5/src/soc/intel/alderlake/acp... File src/soc/intel/alderlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45571/5/src/soc/intel/alderlake/acp... PS5, Line 131: don't we need power management bits here as well?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/5/src/soc/intel/alderlake/acp... File src/soc/intel/alderlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45571/5/src/soc/intel/alderlake/acp... PS5, Line 131:
don't we need power management bits here as well?
can you please help to get an example, so far this is what we provide from GPIO ASL for all SoC.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/5/src/soc/intel/alderlake/acp... File src/soc/intel/alderlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45571/5/src/soc/intel/alderlake/acp... PS5, Line 131:
can you please help to get an example, so far this is what we provide from GPIO ASL for all SoC.
https://review.coreboot.org/c/coreboot/+/34179
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/5/src/soc/intel/alderlake/acp... File src/soc/intel/alderlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45571/5/src/soc/intel/alderlake/acp... PS5, Line 131:
its already here https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/acpi/g...
but you have valid point, few gpio ASL function related to LPIT is missing in TGL too which we can add from CNL to ADL
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45571
to look at the new patch set (#7).
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
soc/intel/alderlake: Add GPIOs for Alder Lake SOC
Add definitions for the GPIO pins on Alder Lake LP, as well as GPIO IRQ routing information and supporting ACPI ASL.
For now, add the following 5 GPIO communities and 13 GPIO groups:
Comm. 0: GPP_B, GPP_T, GPP_A Comm. 1: GPP_S, GPP_H, GPP_D Comm. 2: GPD Comm. 4: GPP_C, GPP_F, GPP_E, GPP_HVMOS Comm. 5: GPP_R, GPP_SPI0
Change-Id: I77b9dcc46aceaf530e2054c9cacd7b026ebbb96b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/acpi/gpio.asl A src/soc/intel/alderlake/gpio.c A src/soc/intel/alderlake/include/soc/gpio.h A src/soc/intel/alderlake/include/soc/gpio_defs.h A src/soc/intel/alderlake/include/soc/gpio_soc_defs.h M src/soc/intel/alderlake/include/soc/pmc.h 7 files changed, 986 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45571/7
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/5/src/soc/intel/alderlake/acp... File src/soc/intel/alderlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45571/5/src/soc/intel/alderlake/acp... PS5, Line 131:
its already here https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/acpi/g.... […]
Ack
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
Angel, please check this https://github.com/coreboot/coreboot/blob/master/src/soc/intel/tigerlake/rom...
This looks like good progress, thanks for sharing. However as usual, FSP UPDs are not acurately documented so we have to guess what it does specifically. There's a hint in the header file it says:
2 - skips GpioSetNativePadByFunction and GpioSetPadMode
But we set it to 1. That at least implies that FSP doesn't skip everything in the current configuration. I wonder if this was another accident, as the commit that added it seemed to assume that is does skip everything.
I'm had refer about SoC default GPIO :) not sure if i have done in mistake conveying the same where FSP also don't touch those GPIOs. ideally no one program those PADs, one could argue, what happen if i want to touch from coreboot, its okay to do i believe as long as its part of EDS, which is not the case, so if like to do randomly knowing there is GPIO COMM 3 and let configure those to NF without knowing the PIN number and description is only my concern.
I completely agree to these concerns. It is always a PITA when one tries to review a change and the necessarry information is missing in the EDS. So please, please, please share your concerns with the people who decide what goes into the EDS and what doesn't. It often seems that it only contains information for OS developers and 80% of the information that would be only for "BIOS" developers is missing. Hiding information from the EDS slows development significantly down.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/5/src/soc/intel/alderlake/acp... File src/soc/intel/alderlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45571/5/src/soc/intel/alderlake/acp... PS5, Line 131:
Ack
Ah, thanks! I missed that
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 7: Code-Review+2
Ok, looks good now :-)
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 7:
Patch Set 7: Code-Review+2
Ok, looks good now :-)
:) thanks for suggestion
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
soc/intel/alderlake: Add GPIOs for Alder Lake SOC
Add definitions for the GPIO pins on Alder Lake LP, as well as GPIO IRQ routing information and supporting ACPI ASL.
For now, add the following 5 GPIO communities and 13 GPIO groups:
Comm. 0: GPP_B, GPP_T, GPP_A Comm. 1: GPP_S, GPP_H, GPP_D Comm. 2: GPD Comm. 4: GPP_C, GPP_F, GPP_E, GPP_HVMOS Comm. 5: GPP_R, GPP_SPI0
Change-Id: I77b9dcc46aceaf530e2054c9cacd7b026ebbb96b Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45571 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/acpi/gpio.asl A src/soc/intel/alderlake/gpio.c A src/soc/intel/alderlake/include/soc/gpio.h A src/soc/intel/alderlake/include/soc/gpio_defs.h A src/soc/intel/alderlake/include/soc/gpio_soc_defs.h M src/soc/intel/alderlake/include/soc/pmc.h 7 files changed, 986 insertions(+), 12 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index a0b0e36..7ea9301 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -12,11 +12,18 @@ bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c +bootblock-y += gpio.c bootblock-y += p2sb.c
romstage-y += espi.c +romstage-y += gpio.c romstage-y += meminit.c romstage-y += reset.c + +ramstage-y += gpio.c + +smm-y += gpio.c + CPPFLAGS_common += -I$(src)/soc/intel/alderlake CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include endif diff --git a/src/soc/intel/alderlake/acpi/gpio.asl b/src/soc/intel/alderlake/acpi/gpio.asl new file mode 100644 index 0000000..e21f6d5 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/gpio.asl @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <intelblocks/gpio.h> +#include <soc/gpio_defs.h> +#include <soc/intel/common/acpi/gpio.asl> +#include <soc/intel/common/block/acpi/acpi/gpio_op.asl> +#include <soc/irq.h> +#include <soc/pcr_ids.h> + +Device (GPIO) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 0) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE + + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE + + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE + + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + BAS5 = ^^PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END) + { + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPIO_COM0_START + } + /* GPIO Community 1 */ + If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END) + { + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPIO_COM1_START + } + /* GPIO Community 2 */ + If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END) + { + Local0 = PID_GPIOCOM2 + Local1 = Arg0 - GPIO_COM2_START + } + /* GPIO Community 4 */ + If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END) + { + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPIO_COM4_START + } + /* GPIO Community 5*/ + If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END) + { + Local0 = PID_GPIOCOM5 + Local1 = Arg0 - GPIO_COM5_START + } + + Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) + Return (Local2) +} + +/* + * Return PCR Port ID of GPIO Communities + * + * Arg0: GPIO Community (0-5) + */ +Method (GPID, 1, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (COMM_0) { + Local0 = PID_GPIOCOM0 + } + Case (COMM_1) { + Local0 = PID_GPIOCOM1 + } + Case (COMM_2) { + Local0 = PID_GPIOCOM2 + } + Case (COMM_4) { + Local0 = PID_GPIOCOM4 + } + Case (COMM_5) { + Local0 = PID_GPIOCOM5 + } + Default { + Return (0) + } + } + + Return (Local0) +} + +/* GPIO Power Management bits */ +Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0}) + +/* + * Save GPIO Power Management bits + */ +Method (SGPM, 0, Serialized) +{ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + Local1 = GPID (Local0) + GPMB[Local0] = PCRR (Local1, GPIO_MISCCFG) + } +} + +/* + * Restore GPIO Power Management bits + */ +Method (RGPM, 0, Serialized) +{ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + CGPM (Local0, DerefOf(GPMB[Local0])) + } +} + +/* + * Save current setting of GPIO Power Management bits and + * enable all Power Management bits for all communities + */ +Method (EGPM, 0, Serialized) +{ + /* Save current setting and will restore it when resuming */ + SGPM () + /* Enable PM bits */ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + CGPM (Local0, MISCCFG_ENABLE_GPIO_PM_CONFIG) + } +} diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c new file mode 100644 index 0000000..f0db5e9 --- /dev/null +++ b/src/soc/intel/alderlake/gpio.c @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/gpio.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> +#include <soc/pmc.h> + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 630094 + * Chapter number: 27 + */ + +static const struct reset_mapping rst_map[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, +}; +static const struct reset_mapping rst_map_com2[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, +}; + +/* + * The GPIO pinctrl driver for Alder Lake on Linux expects 32 GPIOs per pad + * group, regardless of whether or not there is a physical pad for each + * exposed GPIO number. + * + * This results in the OS having a sparse GPIO map, and devices that need + * to export an ACPI GPIO must use the OS expected number. + * + * Not all pins are usable as GPIO and those groups do not have a pad base. + */ +static const struct pad_group adl_community0_groups[] = { + INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B25, 0), /* GPP_B */ + INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 32), /* GPP_T */ + INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_ESPI_CLK_LOOPBK, 64), /* GPP_A */ +}; + +static const struct pad_group adl_community1_groups[] = { + INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */ + INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128), /* GPP_H */ + INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160), /* GPP_D */ +}; + +/* This community is not visible to the OS */ +static const struct pad_group adl_community2_groups[] = { + INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */ +}; + +static const struct pad_group adl_community4_groups[] = { + INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */ + INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288), /* GPP_F */ + INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB), /* GPP_HVMOS */ + INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320), /* GPP_E */ +}; + +static const struct pad_group adl_community5_groups[] = { + INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352), /* GPP_R */ + INTEL_GPP(GPP_R0, GPP_SPI0_IO_2, GPP_SPI0_CLK), /* GPP_SPI0 */ +}; + +static const struct pad_community adl_communities[] = { + [COMM_0] = { /* GPP B, T, A */ + .port = PID_GPIOCOM0, + .first_pad = GPIO_COM0_START, + .last_pad = GPIO_COM0_END, + .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_BTA", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = adl_community0_groups, + .num_groups = ARRAY_SIZE(adl_community0_groups), + }, + [COMM_1] = { /* GPP S, D, H */ + .port = PID_GPIOCOM1, + .first_pad = GPIO_COM1_START, + .last_pad = GPIO_COM1_END, + .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_SDH", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = adl_community1_groups, + .num_groups = ARRAY_SIZE(adl_community1_groups), + }, + [COMM_2] = { /* GPD */ + .port = PID_GPIOCOM2, + .first_pad = GPIO_COM2_START, + .last_pad = GPIO_COM2_END, + .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPD", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map_com2, + .num_reset_vals = ARRAY_SIZE(rst_map_com2), + .groups = adl_community2_groups, + .num_groups = ARRAY_SIZE(adl_community2_groups), + }, + [COMM_4] = { /* GPP F, C, HVMOS, E */ + .port = PID_GPIOCOM4, + .first_pad = GPIO_COM4_START, + .last_pad = GPIO_COM4_END, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_FCE", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = adl_community4_groups, + .num_groups = ARRAY_SIZE(adl_community4_groups), + }, + [COMM_5] = { /* GPP R, SPI0 */ + .port = PID_GPIOCOM5, + .first_pad = GPIO_COM5_START, + .last_pad = GPIO_COM5_END, + .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_RSPI0", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = adl_community5_groups, + .num_groups = ARRAY_SIZE(adl_community5_groups), + } +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(adl_communities); + return adl_communities; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + static const struct pmc_to_gpio_route routes[] = { + { PMC_GPP_B, GPP_B }, + { PMC_GPP_T, GPP_T }, + { PMC_GPP_A, GPP_A }, + { PMC_GPP_S, GPP_S }, + { PMC_GPP_H, GPP_H }, + { PMC_GPP_D, GPP_D }, + { PMC_GPD, GPD }, + { PMC_GPP_C, GPP_C }, + { PMC_GPP_F, GPP_F }, + { PMC_GPP_HVMOS, GPP_HVMOS }, + { PMC_GPP_E, GPP_E }, + { PMC_GPP_R, GPP_R }, + { PMC_GPP_SPI0, GPP_SPI0 }, + }; + *num = ARRAY_SIZE(routes); + return routes; +} diff --git a/src/soc/intel/alderlake/include/soc/gpio.h b/src/soc/intel/alderlake/include/soc/gpio.h new file mode 100644 index 0000000..eec698a --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_GPIO_H_ +#define _SOC_ALDERLAKE_GPIO_H_ + +#include <soc/gpio_defs.h> +#include <intelblocks/gpio.h> + +#define CROS_GPIO_NAME "INTC1055" +#define CROS_GPIO_DEVICE_NAME "INTC1055:00" + +#endif diff --git a/src/soc/intel/alderlake/include/soc/gpio_defs.h b/src/soc/intel/alderlake/include/soc/gpio_defs.h new file mode 100644 index 0000000..68b886a --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/gpio_defs.h @@ -0,0 +1,273 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_GPIO_DEFS_H_ +#define _SOC_ALDERLAKE_GPIO_DEFS_H_ + +#ifndef __ACPI__ +#include <stddef.h> +#endif +#include <soc/gpio_soc_defs.h> + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group T */ +#define GPP_T0_IRQ 0x30 +#define GPP_T1_IRQ 0x31 +#define GPP_T2_IRQ 0x32 +#define GPP_T3_IRQ 0x33 +#define GPP_T4_IRQ 0x34 +#define GPP_T5_IRQ 0x35 +#define GPP_T6_IRQ 0x36 +#define GPP_T7_IRQ 0x37 +#define GPP_T8_IRQ 0x38 +#define GPP_T9_IRQ 0x39 +#define GPP_T10_IRQ 0x3A +#define GPP_T11_IRQ 0x3B +#define GPP_T12_IRQ 0x3C +#define GPP_T13_IRQ 0x3D +#define GPP_T14_IRQ 0x3E +#define GPP_T15_IRQ 0x3F + +/* Group A */ +#define GPP_A0_IRQ 0x40 +#define GPP_A1_IRQ 0x41 +#define GPP_A2_IRQ 0x42 +#define GPP_A3_IRQ 0x43 +#define GPP_A4_IRQ 0x44 +#define GPP_A5_IRQ 0x45 +#define GPP_A6_IRQ 0x46 +#define GPP_A7_IRQ 0x47 +#define GPP_A8_IRQ 0x48 +#define GPP_A9_IRQ 0x49 +#define GPP_A10_IRQ 0x4A +#define GPP_A11_IRQ 0x4B +#define GPP_A12_IRQ 0x4C +#define GPP_A13_IRQ 0x4D +#define GPP_A14_IRQ 0x4E +#define GPP_A15_IRQ 0x4F +#define GPP_A16_IRQ 0x50 +#define GPP_A17_IRQ 0x51 +#define GPP_A18_IRQ 0x52 +#define GPP_A19_IRQ 0x53 +#define GPP_A20_IRQ 0x54 +#define GPP_A21_IRQ 0x55 +#define GPP_A22_IRQ 0x56 +#define GPP_A23_IRQ 0x57 + +/* Group B */ +#define GPP_B0_IRQ 0x18 +#define GPP_B1_IRQ 0x19 +#define GPP_B2_IRQ 0x1A +#define GPP_B3_IRQ 0x1B +#define GPP_B4_IRQ 0x1C +#define GPP_B5_IRQ 0x1D +#define GPP_B6_IRQ 0x1E +#define GPP_B7_IRQ 0x1F +#define GPP_B8_IRQ 0x20 +#define GPP_B9_IRQ 0x21 +#define GPP_B10_IRQ 0x22 +#define GPP_B11_IRQ 0x23 +#define GPP_B12_IRQ 0x24 +#define GPP_B13_IRQ 0x25 +#define GPP_B14_IRQ 0x26 +#define GPP_B15_IRQ 0x27 +#define GPP_B16_IRQ 0x28 +#define GPP_B17_IRQ 0x29 +#define GPP_B18_IRQ 0x2A +#define GPP_B19_IRQ 0x2B +#define GPP_B20_IRQ 0x2C +#define GPP_B21_IRQ 0x2D +#define GPP_B22_IRQ 0x2E +#define GPP_B23_IRQ 0x2F + +/* Group C */ +#define GPP_C0_iIRQ 0x6E +#define GPP_C1_IRQ 0x6F +#define GPP_C2_IRQ 0x70 +#define GPP_C3_IRQ 0x71 +#define GPP_C4_IRQ 0x72 +#define GPP_C5_IRQ 0x73 +#define GPP_C6_IRQ 0x74 +#define GPP_C7_IRQ 0x75 +#define GPP_C8_IRQ 0x76 +#define GPP_C9_IRQ 0x77 +#define GPP_C10_IRQ 0x18 +#define GPP_C11_IRQ 0x19 +#define GPP_C12_IRQ 0x1A +#define GPP_C13_IRQ 0x1B +#define GPP_C14_IRQ 0x1C +#define GPP_C15_IRQ 0x1D +#define GPP_C16_IRQ 0x1E +#define GPP_C17_IRQ 0x1F +#define GPP_C18_IRQ 0x20 +#define GPP_C19_IRQ 0x21 +#define GPP_C20_IRQ 0x22 +#define GPP_C21_IRQ 0x23 +#define GPP_C22_IRQ 0x24 +#define GPP_C23_IRQ 0x25 + +/* Group D */ +#define GPP_D0_IRQ 0x2C +#define GPP_D1_IRQ 0x2D +#define GPP_D2_IRQ 0x2E +#define GPP_D3_IRQ 0x2F +#define GPP_D4_IRQ 0x30 +#define GPP_D5_IRQ 0x31 +#define GPP_D6_IRQ 0x32 +#define GPP_D7_IRQ 0x33 +#define GPP_D8_IRQ 0x34 +#define GPP_D9_IRQ 0x35 +#define GPP_D10_IRQ 0x36 +#define GPP_D11_IRQ 0x37 +#define GPP_D12_IRQ 0x38 +#define GPP_D13_IRQ 0x39 +#define GPP_D14_IRQ 0x3A +#define GPP_D15_IRQ 0x3B +#define GPP_D16_IRQ 0x3C +#define GPP_D17_IRQ 0x3D +#define GPP_D18_IRQ 0x3E +#define GPP_D19_IRQ 0x3F + +/* Group E */ +#define GPP_E0_IRQ 0x26 +#define GPP_E1_IRQ 0x27 +#define GPP_E2_IRQ 0x28 +#define GPP_E3_IRQ 0x29 +#define GPP_E4_IRQ 0x30 +#define GPP_E5_IRQ 0x31 +#define GPP_E6_IRQ 0x32 +#define GPP_E7_IRQ 0x33 +#define GPP_E8_IRQ 0x34 +#define GPP_E9_IRQ 0x35 +#define GPP_E10_IRQ 0x36 +#define GPP_E11_IRQ 0x37 +#define GPP_E12_IRQ 0x38 +#define GPP_E13_IRQ 0x39 +#define GPP_E14_IRQ 0x3A +#define GPP_E15_IRQ 0x3B +#define GPP_E16_IRQ 0x3C +#define GPP_E17_IRQ 0x3D +#define GPP_E18_IRQ 0x3E +#define GPP_E19_IRQ 0x3F +#define GPP_E20_IRQ 0x40 +#define GPP_E21_IRQ 0x41 +#define GPP_E22_IRQ 0x42 +#define GPP_E23_IRQ 0x43 + +/* Group F */ +#define GPP_F0_IRQ 0x56 +#define GPP_F1_IRQ 0x57 +#define GPP_F2_IRQ 0x58 +#define GPP_F3_IRQ 0x59 +#define GPP_F4_IRQ 0x5A +#define GPP_F5_IRQ 0x5B +#define GPP_F6_IRQ 0x5C +#define GPP_F7_IRQ 0x5D +#define GPP_F8_IRQ 0x5E +#define GPP_F9_IRQ 0x5F +#define GPP_F10_IRQ 0x60 +#define GPP_F11_IRQ 0x61 +#define GPP_F12_IRQ 0x62 +#define GPP_F13_IRQ 0x63 +#define GPP_F14_IRQ 0x64 +#define GPP_F15_IRQ 0x65 +#define GPP_F16_IRQ 0x66 +#define GPP_F17_IRQ 0x67 +#define GPP_F18_IRQ 0x68 +#define GPP_F19_IRQ 0x69 +#define GPP_F20_IRQ 0x6A +#define GPP_F21_IRQ 0x6B +#define GPP_F22_IRQ 0x6C +#define GPP_F23_IRQ 0x6D + +/* Group H */ +#define GPP_H0_IRQ 0x74 +#define GPP_H1_IRQ 0x75 +#define GPP_H2_IRQ 0x76 +#define GPP_H3_IRQ 0x77 +#define GPP_H4_IRQ 0x18 +#define GPP_H5_IRQ 0x19 +#define GPP_H6_IRQ 0x1A +#define GPP_H7_IRQ 0x1B +#define GPP_H8_IRQ 0x1C +#define GPP_H9_IRQ 0x1D +#define GPP_H10_IRQ 0x1E +#define GPP_H11_IRQ 0x1F +#define GPP_H12_IRQ 0x20 +#define GPP_H13_IRQ 0x21 +#define GPP_H14_IRQ 0x22 +#define GPP_H15_IRQ 0x23 +#define GPP_H16_IRQ 0x24 +#define GPP_H17_IRQ 0x25 +#define GPP_H18_IRQ 0x26 +#define GPP_H19_IRQ 0x27 +#define GPP_H20_IRQ 0x28 +#define GPP_H21_IRQ 0x29 +#define GPP_H22_IRQ 0x2A +#define GPP_H23_IRQ 0x2B + +/* Group R */ +#define GPP_R0_IRQ 0x58 +#define GPP_R1_IRQ 0x59 +#define GPP_R2_IRQ 0x5A +#define GPP_R3_IRQ 0x5B +#define GPP_R4_IRQ 0x5C +#define GPP_R5_IRQ 0x5D +#define GPP_R6_IRQ 0x5E +#define GPP_R7_IRQ 0x5F + +/* Group S */ +#define GPP_S0_IRQ 0x6C +#define GPP_S1_IRQ 0x6D +#define GPP_S2_IRQ 0x6E +#define GPP_S3_IRQ 0x6F +#define GPP_S4_IRQ 0x70 +#define GPP_S5_IRQ 0x71 +#define GPP_S6_IRQ 0x72 +#define GPP_S7_IRQ 0x73 + +/* Group GPD */ +#define GPD0_IRQ 0x60 +#define GPD1_IRQ 0x61 +#define GPD2_IRQ 0x62 +#define GPD3_IRQ 0x63 +#define GPD4_IRQ 0x64 +#define GPD5_IRQ 0x65 +#define GPD6_IRQ 0x66 +#define GPD7_IRQ 0x67 +#define GPD8_IRQ 0x68 +#define GPD9_IRQ 0x69 +#define GPD10_IRQ 0x6A +#define GPD11_IRQ 0x6B + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x110 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1A0 +#define PAD_CFG_BASE 0x700 + +#endif diff --git a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h new file mode 100644 index 0000000..bf95716 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _SOC_ALDERLAKE_GPIO_SOC_DEFS_H_ +#define _SOC_ALDERLAKE_GPIO_SOC_DEFS_H_ + +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ +/* GPIO COMM 0 */ +#define GPP_B 0x0 +#define GPP_T 0x1 +#define GPP_A 0x2 +/* GPIO COMM 1 */ +#define GPP_S 0x3 +#define GPP_H 0x4 +#define GPP_D 0x5 +/* GPIO COMM 2 */ +#define GPD 0x6 +/* GPIO COMM 4 */ +#define GPP_C 0x7 +#define GPP_F 0x8 +#define GPP_HVMOS 0x9 +#define GPP_E 0xA +/* GPIO COMM 5 */ +#define GPP_R 0xB +#define GPP_SPI0 0xC + +#define GPIO_MAX_NUM_PER_GROUP 26 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +/* GPIO community 3 is not exposed to be used and hence is skipped. */ +#define COMM_4 3 +#define COMM_5 4 +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ +/* Group B */ +#define GPP_B0 0 +#define GPP_B1 1 +#define GPP_B2 2 +#define GPP_B3 3 +#define GPP_B4 4 +#define GPP_B5 5 +#define GPP_B6 6 +#define GPP_B7 7 +#define GPP_B8 8 +#define GPP_B9 9 +#define GPP_B10 10 +#define GPP_B11 11 +#define GPP_B12 12 +#define GPP_B13 13 +#define GPP_B14 14 +#define GPP_B15 15 +#define GPP_B16 16 +#define GPP_B17 17 +#define GPP_B18 18 +#define GPP_B19 19 +#define GPP_B20 20 +#define GPP_B21 21 +#define GPP_B22 22 +#define GPP_B23 23 +#define GPP_B24 24 /* GSPI0_CLK_LOOPBK */ +#define GPP_B25 25 /* GSPI1_CLK_LOOPBK */ + +/* Group T */ +#define GPP_T0 26 +#define GPP_T1 27 +#define GPP_T2 28 +#define GPP_T3 29 +#define GPP_T4 30 +#define GPP_T5 31 +#define GPP_T6 32 +#define GPP_T7 33 +#define GPP_T8 34 +#define GPP_T9 35 +#define GPP_T10 36 +#define GPP_T11 37 +#define GPP_T12 38 +#define GPP_T13 39 +#define GPP_T14 40 +#define GPP_T15 41 + +/* Group A */ +#define GPP_A0 42 +#define GPP_A1 43 +#define GPP_A2 44 +#define GPP_A3 45 +#define GPP_A4 46 +#define GPP_A5 47 +#define GPP_A6 48 +#define GPP_A7 49 +#define GPP_A8 50 +#define GPP_A9 51 +#define GPP_A10 52 +#define GPP_A11 53 +#define GPP_A12 54 +#define GPP_A13 55 +#define GPP_A14 56 +#define GPP_A15 57 +#define GPP_A16 58 +#define GPP_A17 59 +#define GPP_A18 60 +#define GPP_A19 61 +#define GPP_A20 62 +#define GPP_A21 63 +#define GPP_A22 64 +#define GPP_A23 65 +#define GPP_ESPI_CLK_LOOPBK 66 + +#define GPIO_COM0_START GPP_B0 +#define GPIO_COM0_END GPP_ESPI_CLK_LOOPBK +#define NUM_GPIO_COM0_PADS (GPIO_COM0_END - GPIO_COM0_START + 1) + +/* Group S */ +#define GPP_S0 67 +#define GPP_S1 68 +#define GPP_S2 69 +#define GPP_S3 70 +#define GPP_S4 71 +#define GPP_S5 72 +#define GPP_S6 73 +#define GPP_S7 74 + +/* Group H */ +#define GPP_H0 75 +#define GPP_H1 76 +#define GPP_H2 77 +#define GPP_H3 78 +#define GPP_H4 79 +#define GPP_H5 80 +#define GPP_H6 81 +#define GPP_H7 82 +#define GPP_H8 83 +#define GPP_H9 84 +#define GPP_H10 85 +#define GPP_H11 86 +#define GPP_H12 87 +#define GPP_H13 88 +#define GPP_H14 89 +#define GPP_H15 90 +#define GPP_H16 91 +#define GPP_H17 92 +#define GPP_H18 93 +#define GPP_H19 94 +#define GPP_H20 95 +#define GPP_H21 96 +#define GPP_H22 97 +#define GPP_H23 98 + +/* Group D */ +#define GPP_D0 99 +#define GPP_D1 100 +#define GPP_D2 101 +#define GPP_D3 102 +#define GPP_D4 103 +#define GPP_D5 104 +#define GPP_D6 105 +#define GPP_D7 106 +#define GPP_D8 107 +#define GPP_D9 108 +#define GPP_D10 109 +#define GPP_D11 110 +#define GPP_D12 111 +#define GPP_D13 112 +#define GPP_D14 113 +#define GPP_D15 114 +#define GPP_D16 115 +#define GPP_D17 116 +#define GPP_D18 117 +#define GPP_D19 118 +#define GPP_GSPI2_CLK_LOOPBK 119 + +#define GPIO_COM1_START GPP_S0 +#define GPIO_COM1_END GPP_GSPI2_CLK_LOOPBK +#define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1) + +/* Group GPD */ +#define GPD0 120 +#define GPD1 121 +#define GPD2 122 +#define GPD3 123 +#define GPD4 124 +#define GPD5 125 +#define GPD6 126 +#define GPD7 127 +#define GPD8 128 +#define GPD9 129 +#define GPD10 130 +#define GPD11 131 +#define GPD_INPUT3VSEL 132 +#define GPD_SLP_LANB 133 +#define GPD_SLP_SUSB 134 +#define GPD_WAKEB 135 +#define GPD_DRAM_RESETB 136 + +#define GPIO_COM2_START GPD0 +#define GPIO_COM2_END GPD_DRAM_RESETB +#define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1) + +/* Group C */ +#define GPP_C0 137 +#define GPP_C1 138 +#define GPP_C2 139 +#define GPP_C3 140 +#define GPP_C4 141 +#define GPP_C5 142 +#define GPP_C6 143 +#define GPP_C7 144 +#define GPP_C8 145 +#define GPP_C9 146 +#define GPP_C10 147 +#define GPP_C11 148 +#define GPP_C12 149 +#define GPP_C13 150 +#define GPP_C14 151 +#define GPP_C15 152 +#define GPP_C16 153 +#define GPP_C17 154 +#define GPP_C18 155 +#define GPP_C19 156 +#define GPP_C20 157 +#define GPP_C21 158 +#define GPP_C22 159 +#define GPP_C23 160 + +/* Group F */ +#define GPP_F0 161 +#define GPP_F1 162 +#define GPP_F2 163 +#define GPP_F3 164 +#define GPP_F4 165 +#define GPP_F5 166 +#define GPP_F6 167 +#define GPP_F7 168 +#define GPP_F8 169 +#define GPP_F9 170 +#define GPP_F10 171 +#define GPP_F11 172 +#define GPP_F12 173 +#define GPP_F13 174 +#define GPP_F14 175 +#define GPP_F15 176 +#define GPP_F16 177 +#define GPP_F17 178 +#define GPP_F18 179 +#define GPP_F19 180 +#define GPP_F20 181 +#define GPP_F21 182 +#define GPP_F22 183 +#define GPP_F23 184 +#define GPP_F_CLK_LOOPBK 185 + +/* Group HVMOS */ +#define GPP_L_BKLTEN 186 +#define GPP_L_BKLTCTL 187 +#define GPP_L_VDDEN 188 +#define GPP_SYS_PWROK 189 +#define GPP_SYS_RESETB 190 +#define GPP_MLK_RSTB 191 + +/* Group E */ +#define GPP_E0 192 +#define GPP_E1 193 +#define GPP_E2 194 +#define GPP_E3 195 +#define GPP_E4 196 +#define GPP_E5 197 +#define GPP_E6 198 +#define GPP_E7 199 +#define GPP_E8 200 +#define GPP_E9 201 +#define GPP_E10 202 +#define GPP_E11 203 +#define GPP_E12 204 +#define GPP_E13 205 +#define GPP_E14 206 +#define GPP_E15 207 +#define GPP_E16 208 +#define GPP_E17 209 +#define GPP_E18 210 +#define GPP_E19 211 +#define GPP_E20 212 +#define GPP_E21 213 +#define GPP_E22 214 +#define GPP_E23 215 +#define GPP_E_CLK_LOOPBK 216 + +#define GPIO_COM4_START GPP_C0 +#define GPIO_COM4_END GPP_E_CLK_LOOPBK +#define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1) + +/* Group R */ +#define GPP_R0 217 +#define GPP_R1 218 +#define GPP_R2 219 +#define GPP_R3 220 +#define GPP_R4 221 +#define GPP_R5 222 +#define GPP_R6 223 +#define GPP_R7 224 + +/* Group SPI0 */ +#define GPP_SPI0_IO_2 225 +#define GPP_SPI0_IO_3 226 +#define GPP_SPI0_MOSI_IO_0 227 +#define GPP_SPI0_MOSI_IO_1 228 +#define GPP_SPI0_TPM_CSB 229 +#define GPP_SPI0_FLASH_0_CSB 230 +#define GPP_SPI0_FLASH_1_CSB 231 +#define GPP_SPI0_CLK 232 + +#define GPIO_COM5_START GPP_R0 +#define GPIO_COM5_END GPP_SPI0_CLK +#define NUM_GPIO_COM5_PADS (GPIO_COM5_END - GPIO_COM5_START + 1) + +#define TOTAL_GPIO_COMM (COMM_5 + 1) +#define TOTAL_PADS (GPIO_COM5_END + 1) + +#endif diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h index f110070..03fe02f 100644 --- a/src/soc/intel/alderlake/include/soc/pmc.h +++ b/src/soc/intel/alderlake/include/soc/pmc.h @@ -126,18 +126,19 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x))
-#define PMC_GPP_B 0x0 -#define PMC_GPP_T 0x1 -#define PMC_GPP_A 0x2 -#define PMC_GPP_R 0x3 -#define PMC_GPD 0x4 -#define PMC_GPP_S 0x5 -#define PMC_GPP_H 0x6 -#define PMC_GPP_D 0x7 -#define PMC_GPP_U 0x8 -#define PMC_GPP_F 0xA -#define PMC_GPP_C 0xB -#define PMC_GPP_E 0xC +#define PMC_GPP_B 0x0 +#define PMC_GPP_T 0x1 +#define PMC_GPP_A 0x2 +#define PMC_GPP_S 0x3 +#define PMC_GPP_H 0x4 +#define PMC_GPP_D 0x5 +#define PMC_GPD 0x6 +#define PMC_GPP_C 0x7 +#define PMC_GPP_F 0x8 +#define PMC_GPP_HVMOS 0x9 +#define PMC_GPP_E 0xA +#define PMC_GPP_R 0xB +#define PMC_GPP_SPI0 0xC
#define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5)
Attention is currently required from: Subrata Banik. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 8:
(2 comments)
File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/comment/764db002_b475874c PS8, Line 10: /* GPIO COMM 0 */ : #define GPP_B 0x0 : #define GPP_T 0x1 : #define GPP_A 0x2 : /* GPIO COMM 1 */ : #define GPP_S 0x3 : #define GPP_H 0x4 : #define GPP_D 0x5 : /* GPIO COMM 2 */ : #define GPD 0x6 : /* GPIO COMM 4 */ : #define GPP_C 0x7 : #define GPP_F 0x8 : #define GPP_HVMOS 0x9 : #define GPP_E 0xA : /* GPIO COMM 5 */ : #define GPP_R 0xB : #define GPP_SPI0 0xC : These are wrong. They do not match PCH EDS Vol 2 v1.0.
File src/soc/intel/alderlake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/45571/comment/f0fb61dc_b8c290f7 PS8, Line 128: : #define PMC_GPP_B 0x0 : #define PMC_GPP_T 0x1 : #define PMC_GPP_A 0x2 : #define PMC_GPP_S 0x3 : #define PMC_GPP_H 0x4 : #define PMC_GPP_D 0x5 : #define PMC_GPD 0x6 : #define PMC_GPP_C 0x7 : #define PMC_GPP_F 0x8 : #define PMC_GPP_HVMOS 0x9 : #define PMC_GPP_E 0xA : #define PMC_GPP_R 0xB : #define PMC_GPP_SPI0 0xC These are wrong. They do not match PCH EDS Vol 2 v1.0.
Attention is currently required from: Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/comment/ba9893db_c67a362e PS8, Line 10: /* GPIO COMM 0 */ : #define GPP_B 0x0 : #define GPP_T 0x1 : #define GPP_A 0x2 : /* GPIO COMM 1 */ : #define GPP_S 0x3 : #define GPP_H 0x4 : #define GPP_D 0x5 : /* GPIO COMM 2 */ : #define GPD 0x6 : /* GPIO COMM 4 */ : #define GPP_C 0x7 : #define GPP_F 0x8 : #define GPP_HVMOS 0x9 : #define GPP_E 0xA : /* GPIO COMM 5 */ : #define GPP_R 0xB : #define GPP_SPI0 0xC :
These are wrong. They do not match PCH EDS Vol 2 v1.0.
Does the EDS agree with my comments on PS2?
Attention is currently required from: Subrata Banik. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/comment/577266b4_e6e5f48d PS8, Line 10: /* GPIO COMM 0 */ : #define GPP_B 0x0 : #define GPP_T 0x1 : #define GPP_A 0x2 : /* GPIO COMM 1 */ : #define GPP_S 0x3 : #define GPP_H 0x4 : #define GPP_D 0x5 : /* GPIO COMM 2 */ : #define GPD 0x6 : /* GPIO COMM 4 */ : #define GPP_C 0x7 : #define GPP_F 0x8 : #define GPP_HVMOS 0x9 : #define GPP_E 0xA : /* GPIO COMM 5 */ : #define GPP_R 0xB : #define GPP_SPI0 0xC :
Does the EDS agree with my comments on PS2?
Comment about GPP_C = 0xb matches. But the others are different.
GPP_F = 0xa, GPP_SPI0/HVMOS are not part of the register values.
and few other differences.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/comment/797c1f95_056407b2 PS8, Line 10: /* GPIO COMM 0 */ : #define GPP_B 0x0 : #define GPP_T 0x1 : #define GPP_A 0x2 : /* GPIO COMM 1 */ : #define GPP_S 0x3 : #define GPP_H 0x4 : #define GPP_D 0x5 : /* GPIO COMM 2 */ : #define GPD 0x6 : /* GPIO COMM 4 */ : #define GPP_C 0x7 : #define GPP_F 0x8 : #define GPP_HVMOS 0x9 : #define GPP_E 0xA : /* GPIO COMM 5 */ : #define GPP_R 0xB : #define GPP_SPI0 0xC :
Comment about GPP_C = 0xb matches. But the others are different. […]
@Furquan, for GPIO COMM 4 GPP_C0 offset start 0x700 - GPP_C23 offset end 0x880 GPP_F0 offset start 0x880 - GPP_CF3 offset 0xA08
EDS says next is GPP_E_0 at offset start 0xA70 and ends at 0xBF0
There is a hole between GPP_F and GPP_E, actually EDS doesn't capture HVMOS because it doesn't have non-board level configuration GPIO, but to make uniform calculation, i have kept that GPIO which was available in internal document.
Same logic for GPP_SPI0 as well.
I don't understand what you mean by wrong here? can you please help ?
Attention is currently required from: Subrata Banik. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/comment/8ba55295_f4969bdd PS8, Line 10: /* GPIO COMM 0 */ : #define GPP_B 0x0 : #define GPP_T 0x1 : #define GPP_A 0x2 : /* GPIO COMM 1 */ : #define GPP_S 0x3 : #define GPP_H 0x4 : #define GPP_D 0x5 : /* GPIO COMM 2 */ : #define GPD 0x6 : /* GPIO COMM 4 */ : #define GPP_C 0x7 : #define GPP_F 0x8 : #define GPP_HVMOS 0x9 : #define GPP_E 0xA : /* GPIO COMM 5 */ : #define GPP_R 0xB : #define GPP_SPI0 0xC :
@Furquan, […]
GPP_* values here must match what is in MISCCFG registers. See section 27.1.3 (Miscellaneous configuration) in PCH EDS Vol 2. It is not based on the offsets of different groups within a community. These get used in configuring MISCCFG registers as part of `gpio_route_gpe()`.
I have raised b/183464235 to track this.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/comment/efafc502_067ccddc PS8, Line 10: /* GPIO COMM 0 */ : #define GPP_B 0x0 : #define GPP_T 0x1 : #define GPP_A 0x2 : /* GPIO COMM 1 */ : #define GPP_S 0x3 : #define GPP_H 0x4 : #define GPP_D 0x5 : /* GPIO COMM 2 */ : #define GPD 0x6 : /* GPIO COMM 4 */ : #define GPP_C 0x7 : #define GPP_F 0x8 : #define GPP_HVMOS 0x9 : #define GPP_E 0xA : /* GPIO COMM 5 */ : #define GPP_R 0xB : #define GPP_SPI0 0xC :
GPP_* values here must match what is in MISCCFG registers. See section 27.1. […]
Thanks Furquan for the details, do you want me to fix this code ?
Attention is currently required from: Subrata Banik. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/comment/d2b6294d_dfa07ca1 PS8, Line 10: /* GPIO COMM 0 */ : #define GPP_B 0x0 : #define GPP_T 0x1 : #define GPP_A 0x2 : /* GPIO COMM 1 */ : #define GPP_S 0x3 : #define GPP_H 0x4 : #define GPP_D 0x5 : /* GPIO COMM 2 */ : #define GPD 0x6 : /* GPIO COMM 4 */ : #define GPP_C 0x7 : #define GPP_F 0x8 : #define GPP_HVMOS 0x9 : #define GPP_E 0xA : /* GPIO COMM 5 */ : #define GPP_R 0xB : #define GPP_SPI0 0xC :
Thanks Furquan for the details, do you want me to fix this code ?
I had assigned the bug to Boris. Let me ping on the bug to see if he needs help or is planning to work on the changes.
-
Angel Pons (Code Review) -
Furquan Shaikh (Code Review)
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Michael Niewöhner (Code Review)
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Nico Huber (Code Review)
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Subrata Banik (Code Review)
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Tim Wawrzynczak (Code Review)