Change in coreboot[master]: mb/google/dedede: Disable dynamic clock gating for cr50's GPIO

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40480 )

Change subject: mb/google/dedede: Disable dynamic clock gating for cr50's GPIO
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mb/google/dedede: Disable dynamic clock gating for cr50's GPIO

Disable dynamic clock gating for the community cr50's IRQ lives on.
That IRQ is pulsed very quickly, and with clock gating enabled pulses
tend to be missed. This is expecially true on the default 0.0.22
firmware that cr50 comes with out of the factory.

BUG=b:154178408 b:154293730
BRANCH=None
TEST=build waddledoo successful and Linux has no TPM IRQ timeout error.

Signed-off-by: Ian Feng 
Change-Id: I2b1b3ee59ebf6adce0653e7550b457e02d3c87df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40480
Tested-by: build bot (Jenkins) 
Reviewed-by: Justin TerAvest 
Reviewed-by: Karthik Ramasubramanian 
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
1 file changed, 8 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Justin TerAvest: Looks good to me, approved
  Karthik Ramasubramanian: Looks good to me, approved

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index f030b20..cfe221f 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -118,6 +118,14 @@
    # Select eDP for port A
    register "DdiPortAConfig" = "1"

+	# Disable PM to allow for shorter irq pulses
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[0]" = "0"
+	register "gpio_pm[1]" = "0"
+	register "gpio_pm[2]" = "0"
+	register "gpio_pm[3]" = "0"
+	register "gpio_pm[4]" = "0"
+
    # Enable HPD for DDI ports B/C
    register "DdiPortBHpd" = "1"
    register "DdiPortCHpd" = "1"