[XS] Change in coreboot[main]: mb/google/nissa/var/sundance: Disable pcie_RP7 setting for S0ix problem

[Roger Wang (Code Review)]

Roger Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83057?usp=email )

Change subject: mb/google/nissa/var/sundance: Disable pcie_RP7 setting for S0ix problem
......................................................................

mb/google/nissa/var/sundance: Disable pcie_RP7 setting for S0ix problem

Disable pcie_RP7 setting to modify system enter S0ix  problem on sundance

BUG=b:328147465
TEST=Build and check S0ix function and verify FAFT sleep funciton.

Change-Id: I53f704ed11a5c63b5c079c6e60ce2fa32bbd8b1a
Signed-off-by: Roger Wang 
---
M src/mainboard/google/brya/variants/sundance/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/83057/1

diff --git a/src/mainboard/google/brya/variants/sundance/overridetree.cb b/src/mainboard/google/brya/variants/sundance/overridetree.cb
index bd5112f..d72755f 100644
--- a/src/mainboard/google/brya/variants/sundance/overridetree.cb
+++ b/src/mainboard/google/brya/variants/sundance/overridetree.cb
@@ -222,6 +222,7 @@
    			device pci 00.0 on end
    		end
    	end
+		device ref pcie_rp7 off end
    	device ref pch_espi on
    		chip ec/google/chromeec
    			use conn0 as mux_conn[0]