Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph, Nico Huber, Martin Roth, Mario Scheithauer, Lean Sheng Tan, Werner Zeh, Felix Held. Hello build bot (Jenkins), Nico Huber, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Michael Niewöhner, Werner Zeh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55367
to look at the new patch set (#57).
Change subject: soc/intel/elkhartlake: Introduce Intel PSE ......................................................................
soc/intel/elkhartlake: Introduce Intel PSE
The Intel® Programmable Services Engine (Intel® PSE) is a dedicated offload engine for IoT functions powered by an ARM Cortex-M7 microcontroller. It provides independent, low-DMIPS computing and low-speed I/Os for IoT applications, plus dedicated services for real-time computing and time-sensitive synchronization.
The PSE hosts new functions, including remote out-of-band device management, network proxy, embedded controller lite and sensor hub.
This CL enables the user to provide the base address of the PSE FW blob which will then be loaded by the FSP-S onto the ARM controller. PSE FW will do the initialization work of PSE controller and its peripherals. The loading of PSE FW should have negligible impact on boot time unless PSE controller could not locate the PSE FW and FSP will attempt to redo PSE FW loading and wait for PSE handshake until it times out. Once PSE controller locate the PSE FW, it will do initialization concurrently by itself with coreboot booting.
It also adds PSE related FSP-S UPD settings which enable the setup of peripheral ownership (assigned to the PSE or x86 subsystem) and interrupts. These assignments need to take place at a given point in the boot process and cannot be changed later.
To verify if PSE FW is loaded properly, the user could enable PchPseShellEnabled flag and the log will be printed at PSE UART 2.
For further info please refer to doc #611825 (for HW overview) and #614110 (for PSE EDS).
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/elkhartlake/romstage/fsp_params.c 5 files changed, 174 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/55367/57
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Lean Sheng Tan (Code Review)