Attention is currently required from: Nico Huber, Tim Wawrzynczak. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49407 )
Change subject: soc/intel/common/gpio: Add gpio_routes_ioapic_irq function ......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/49407/comment/018d4ec5_7a9540d1 PS7, Line 653: gpio_routes_ioapic_irq
I think it would be perfectly legal to program a GPIO for IOAPIC in romstage (perhaps uncommon), but then this would run in ramstage, and not "see" the IOAPIC IRQ.
Early stages are responsible for configuring pads that are used in coreboot until ramstage can perform a full GPIO configuration. Since coreboot does not use IOAPIC or interrupts, configuring pads for IOAPIC in early stages doesn't really make sense. So, I think it is okay to just use the state stashed in ramstage for IOAPIC configuration.
Also, even if we decide to check GPIO table, it would be limited to ramstage only. GPIO tables are not shared across stages. One other complication with looking through GPIO tables is that pads can be configured across multiple tables (base v/s override, fw_config GPIO configuration, configuration within a particular function which could causes misses in ramstage).
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Furquan Shaikh (Code Review)