Andrey Petrov (andrey.petrov@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13348
-gerrit
commit 7fb01b49ae764776865f65709cf0154e5c945e08 Author: Lance Zhao lijian.zhao@intel.com Date: Mon Nov 9 17:06:34 2015 -0800
soc/apollolake: Add skeleton ACPI entry
Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6 Signed-off-by: Lance Zhao lijian.zhao@intel.com --- src/mainboard/intel/apollolake_rvp/Kconfig | 1 + src/mainboard/intel/apollolake_rvp/acpi_tables.c | 17 +++++++++++++ src/mainboard/intel/apollolake_rvp/dsdt.asl | 29 ++++++++++++++++++++++ src/soc/intel/apollolake/Makefile.inc | 31 +++++++++++++----------- src/soc/intel/apollolake/acpi.c | 22 +++++++++++++++++ 5 files changed, 86 insertions(+), 14 deletions(-)
diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 9920b46..5006695 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES
config MAINBOARD_DIR string diff --git a/src/mainboard/intel/apollolake_rvp/acpi_tables.c b/src/mainboard/intel/apollolake_rvp/acpi_tables.c new file mode 100644 index 0000000..9812ac2 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/acpi_tables.c @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ +} diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl new file mode 100644 index 0000000..53f92b4 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + Scope (_SB) { + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) /* PCIe */ + } + } + +} diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4e05726..7efb3ba 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -6,34 +6,37 @@ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/x86/cache
-bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cache_as_ram.S -bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/bootblock_car.c bootblock-y += gpio.c +bootblock-y += bootblock/cache_as_ram.S +bootblock-y += bootblock/early_chipset_config.S bootblock-y += mmap_boot.c -bootblock-y += placeholders.c bootblock-y += tsc_freq.c -bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +bootblock-y += uart_early.c
-romstage-y += placeholders.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c +cpu_incs-y += $(src)/soc/intel/apollolake/romstage/entry.inc romstage-y += gpio.c -romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += memmap.c romstage-y += mmap_boot.c +romstage-y += romstage/romstage.c +romstage-y += tsc_freq.c +romstage-y += uart_early.c
-smm-y += placeholders.c -ramstage-y += cpu.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c -ramstage-y += placeholders.c +ramstage-y += cpu.c ramstage-y += gpio.c -ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += memmap.c ramstage-y += mmap_boot.c +ramstage-y += tsc_freq.c ramstage-y += uart.c -ramstage-y += northbridge.c + +romstage-y += placeholders.c +smm-y += placeholders.c +ramstage-y += placeholders.c + +# cpu_microcode_bins += ???
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c new file mode 100644 index 0000000..b945e40 --- /dev/null +++ b/src/soc/intel/apollolake/acpi.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return 0; +} +unsigned long acpi_fill_madt(unsigned long current) +{ + return 0; +}
-
Andrey Petrov