[S] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree

[Mark Hasemeyer (Code Review)]

Attention is currently required from: Raul Rangel, Jon Murphy, Tim Van Patten, Karthik Ramasubramanian.

Mark Hasemeyer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 )

Change subject: mb/google/myst: Enable PCIe devices in devicetree
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Patch Set 13:

(1 comment)

File src/mainboard/google/myst/variants/baseboard/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/74112/comment/9c606f39_e0638e9f 
PS8, Line 52: 		device ref gpp_bridge_2_4 on end # NVMe
> These are aliases set by the SoC(https://source.chromium. […]

Are the comments correct? The ordering of PCIe nets on the schematic look different. Also NVMe uses 4 lanes. Not sure if that matters here.