Change in coreboot[master]: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/19960 )

Change subject: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM
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Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/19960/2/src/northbridge/intel/sandybridge/ra...
File src/northbridge/intel/sandybridge/raminit_mrc.c:

Line 308: 	ddr_frequency = (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100;
While the same calculation is used on native raminit it is wrong, as of Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c the ref clock can be 100Mhz, resulting in different DDR frequencies.
That has to be addresses in a separate patch.