[M] Change in coreboot[main]: [TEST][WIP]soc/amd: factor out common gpp_clk_setup implementation

[Varshit Pandya (Code Review)]

Varshit Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80285?usp=email )

Change subject: [TEST][WIP]soc/amd: factor out common gpp_clk_setup implementation
......................................................................

[TEST][WIP]soc/amd: factor out common gpp_clk_setup implementation

Starting with PHX

Change-Id: I7d7da4bfe079f07e31212247dbf3acd14daa6447
Signed-off-by: Varshit Pandya 
---
A src/soc/amd/common/block/gpp_clk/Kconfig
A src/soc/amd/common/block/gpp_clk/Makefile.mk
A src/soc/amd/common/block/gpp_clk/gpp_clk.c
A src/soc/amd/common/block/include/amdblocks/gpp_clk.h
M src/soc/amd/phoenix/Kconfig
M src/soc/amd/phoenix/fch.c
6 files changed, 83 insertions(+), 40 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/80285/1

diff --git a/src/soc/amd/common/block/gpp_clk/Kconfig b/src/soc/amd/common/block/gpp_clk/Kconfig
new file mode 100644
index 0000000..eb192ef
--- /dev/null
+++ b/src/soc/amd/common/block/gpp_clk/Kconfig
@@ -0,0 +1,4 @@
+config SOC_AMD_COMMON_BLOCK_GPP_CLK
+	bool
+	help
+	  Select this option to use AMD common GPP support.
diff --git a/src/soc/amd/common/block/gpp_clk/Makefile.mk b/src/soc/amd/common/block/gpp_clk/Makefile.mk
new file mode 100644
index 0000000..3c85d97
--- /dev/null
+++ b/src/soc/amd/common/block/gpp_clk/Makefile.mk
@@ -0,0 +1,2 @@
+## SPDX-License-Identifier: GPL-2.0-only
+ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_GPP_CLK) += gpp_clk.c
diff --git a/src/soc/amd/common/block/gpp_clk/gpp_clk.c b/src/soc/amd/common/block/gpp_clk/gpp_clk.c
new file mode 100644
index 0000000..d6d8610
--- /dev/null
+++ b/src/soc/amd/common/block/gpp_clk/gpp_clk.c
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/gpp_clk.h>
+#include <amdblocks/pci_clk_req.h>
+
+/* configure the general purpose PCIe clock outputs according to the devicetree settings */
+void gpp_clk_setup_common(enum gpp_clk_req *gpp_clk_config, size_t gpp_clk_config_num, int available_clk)
+{
+	/* look-up table to be able to iterate over the PCIe clock output settings */
+	const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = {
+		GPP_CLK0_REQ_SHIFT,
+		GPP_CLK1_REQ_SHIFT,
+		GPP_CLK2_REQ_SHIFT,
+		GPP_CLK3_REQ_SHIFT,
+		GPP_CLK4_REQ_SHIFT,
+		GPP_CLK5_REQ_SHIFT,
+		GPP_CLK6_REQ_SHIFT,
+	};
+
+	uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
+
+	pcie_gpp_dxio_update_clk_req_config(gpp_clk_config, gpp_clk_config_num);
+	for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
+		gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);
+		/*
+		 * The remapping of values is done so that the default of the enum used for the
+		 * devicetree settings is the clock being enabled, so that a missing devicetree
+		 * configuration for this will result in an always active clock and not an
+		 * inactive PCIe clock output. Only the configuration for the clock outputs
+		 * available on the package is provided via the devicetree; the rest is
+		 * switched off unconditionally.
+		 */
+		switch (i < available_clk ? gpp_clk_config[i] : GPP_CLK_OFF) {
+		case GPP_CLK_REQ:
+			gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]);
+			break;
+		case GPP_CLK_OFF:
+			gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]);
+			break;
+		case GPP_CLK_ON:
+		default:
+			gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]);
+		}
+	}
+
+	misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl);
+}
+
diff --git a/src/soc/amd/common/block/include/amdblocks/gpp_clk.h b/src/soc/amd/common/block/include/amdblocks/gpp_clk.h
new file mode 100644
index 0000000..db1cd1a
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/gpp_clk.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_BLOCK_GPP_H
+#define AMD_BLOCK_GPP_H
+
+#include <amdblocks/pci_clk_req.h>
+
+#define	GPP_CLK_CNTRL		0x00
+#define GPP_CLK0_REQ_SHIFT	0
+#define GPP_CLK1_REQ_SHIFT	2
+#define GPP_CLK4_REQ_SHIFT	4
+#define GPP_CLK2_REQ_SHIFT	6
+#define GPP_CLK3_REQ_SHIFT	8
+#define GPP_CLK5_REQ_SHIFT	10
+#define GPP_CLK6_REQ_SHIFT	12
+#define GPP_CLK_OUTPUT_COUNT	7
+#define GPP_CLK_REQ_MASK(clk_shift)	(0x3 << (clk_shift))
+#define GPP_CLK_REQ_ON(clk_shift)	(0x3 << (clk_shift))
+#define GPP_CLK_REQ_EXT(clk_shift)	(0x1 << (clk_shift))
+#define GPP_CLK_REQ_OFF(clk_shift)	(0x0 << (clk_shift))
+
+/* configure the general purpose PCIe clock outputs according to the devicetree settings */
+void gpp_clk_setup_common(enum gpp_clk_req *gpp_clk_config, size_t gpp_clk_config_num, int available_clk);
+
+#endif /* AMD_BLOCK_GPP_H */
diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index fd40231..7d25406 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -44,6 +44,7 @@
    select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT
    select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION
    select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES
+	select SOC_AMD_COMMON_BLOCK_GPP_CLK
    select SOC_AMD_COMMON_BLOCK_GRAPHICS		# TODO: Check if this is still correct
    select SOC_AMD_COMMON_BLOCK_HAS_ESPI
    select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE
diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c
index c2f0558..afda533 100644
--- a/src/soc/amd/phoenix/fch.c
+++ b/src/soc/amd/phoenix/fch.c
@@ -4,6 +4,7 @@
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/amd_pci_util.h>
 #include <amdblocks/gpio.h>
+#include <amdblocks/gpp_clk.h>
 #include <amdblocks/pci_clk_req.h>
 #include <amdblocks/reset.h>
 #include <amdblocks/smi.h>
@@ -126,46 +127,7 @@
 static void gpp_clk_setup(void)
 {
    struct soc_amd_phoenix_config *cfg = config_of_soc();
-
-	/* look-up table to be able to iterate over the PCIe clock output settings */
-	const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = {
-		GPP_CLK0_REQ_SHIFT,
-		GPP_CLK1_REQ_SHIFT,
-		GPP_CLK2_REQ_SHIFT,
-		GPP_CLK3_REQ_SHIFT,
-		GPP_CLK4_REQ_SHIFT,
-		GPP_CLK5_REQ_SHIFT,
-		GPP_CLK6_REQ_SHIFT,
-	};
-
-	uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
-
-	pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0],
-					    ARRAY_SIZE(cfg->gpp_clk_config));
-	for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
-		gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);
-		/*
-		 * The remapping of values is done so that the default of the enum used for the
-		 * devicetree settings is the clock being enabled, so that a missing devicetree
-		 * configuration for this will result in an always active clock and not an
-		 * inactive PCIe clock output. Only the configuration for the clock outputs
-		 * available on the package is provided via the devicetree; the rest is
-		 * switched off unconditionally.
-		 */
-		switch (i < GPP_CLK_OUTPUT_AVAILABLE ? cfg->gpp_clk_config[i] : GPP_CLK_OFF) {
-		case GPP_CLK_REQ:
-			gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]);
-			break;
-		case GPP_CLK_OFF:
-			gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]);
-			break;
-		case GPP_CLK_ON:
-		default:
-			gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]);
-		}
-	}
-
-	misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl);
+	gpp_clk_setup_common(&cfg->gpp_clk_config[0], ARRAY_SIZE(cfg->gpp_clk_config), GPP_CLK_OUTPUT_AVAILABLE);
 }

static void cgpll_clock_gate_init(void)