[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock

[Saurabh Mishra (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun.

Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
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Patch Set 31:

(8 comments)

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83354/comment/9a31e5a5_ccb35894?usp... :
PS30, Line 141: 0xfe02c000
> what is the reason behind changing the UART base address ?

We have matched with PTL FSP base address. This setting ensures the FSP's setting right IRQ to LPSS will be used by the coreboot.

File src/soc/intel/pantherlake/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/d7709d76_7b2acca4?usp... :
PS30, Line 17:
>

Acknowledged

https://review.coreboot.org/c/coreboot/+/83354/comment/e2064711_4db9587d?usp... :
PS30, Line 18: 0xfa000000
> as per FAS "SAFBAR will be moved to above 4GB", I could see the BAR is above 4GB as per FAS

Corrected.

https://review.coreboot.org/c/coreboot/+/83354/comment/1fd2ad5f_9eff9365?usp... :
PS30, Line 18:
> use tab

Acknowledged

https://review.coreboot.org/c/coreboot/+/83354/comment/fbdcd0aa_b4b87d5e?usp... :
PS30, Line 19:
> same

Acknowledged

https://review.coreboot.org/c/coreboot/+/83354/comment/eae218e9_4e2df62b?usp... :
PS30, Line 46:
> use tab

Acknowledged

File src/soc/intel/pantherlake/include/soc/pcr_ids.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/c4a54516_0afeeedd?usp... :
PS30, Line 6: ids
> IDs?

Acknowledged

File src/soc/intel/pantherlake/include/soc/pm.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/9c655af8_88044c28?usp... :
PS30, Line 7: WAK_STS		BIT(15)
            : #define  PCIEXPWAK_STS		BIT(14)
            : #define  PRBTNOR_STS		BIT(11)
            : #define  RTC_STS		BIT(10)
            : #define  PWRBTN_STS		BIT(8)
            : #define  GBL_STS		BIT(5)
            : #define  BM_STS			BIT(4)
            : #define  TMROF_STS		BIT(0)
> use one space to start with because these are the bit fields of PM1_STS […]

Acknowledged