Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36684 )
Change subject: src/soc/intel: Add Cometlake-S and CMP-H skus ......................................................................
src/soc/intel: Add Cometlake-S and CMP-H skus
This patch adds some sku support for CML-S CPU and CMP-H chips. According to doc #605546: CML-S (6+2) G0: A0650h CML-S (6+2) G1: A0653h CML-S (10+2) P0: A0651h CML-S (10+2) Q0/P1: A0654h
CMP-H HM470: 068Dh CMP-H WM490: 068Eh CMP-H QM480: 068Ch CMP-H H470: 0684h CMP-H Z490: 0685h CMP-H Q470: 0687h
TEST=Boot with CML-S (6+2) G1 + CMP-H WM490 and IDs are recognized
Change-Id: I6bda09070ec330033eff95329448ace57e87144f Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com --- M 3rdparty/blobs M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/systemagent/systemagent.c 7 files changed, 44 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/36684/1
diff --git a/3rdparty/blobs b/3rdparty/blobs index 62aa0e0..8fd95cb 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 62aa0e0c54295bbb7b1a3e5e73f960bafdb59d04 +Subproject commit 8fd95cbe886c0dd0eb2a9b8c99bfea2a19d53750 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 4d21f5b..1037705 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2767,6 +2767,13 @@ #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284 #define PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC 0x0285 #define PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC 0x0286 +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_HM470 0x068D +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_WM490 0x068E +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_QM480 0x068C +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_W480 0x0697 +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_H470 0x0684 +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_Z490 0x0685 +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_Q470 0x0687 #define PCI_DEVICE_ID_INTEL_TGL_ESPI 0xA083
/* Intel PCIE device ids */ @@ -3229,6 +3236,10 @@ #define PCI_DEVICE_ID_INTEL_CML_GT1_H_2 0x9B22 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_1 0x9B44 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_2 0x9B42 +#define PCI_DEVICE_ID_INTEL_CML_GT2_S_G0 0x9BC8 +#define PCI_DEVICE_ID_INTEL_CML_GT2_S_P0 0x9BC5 +#define PCI_DEVICE_ID_INTEL_CML_GT2_H_R0 0x3E9B +#define PCI_DEVICE_ID_INTEL_CML_GT2_H_R1 0x9BC4 #define PCI_DEVICE_ID_INTEL_TGL_GT1 0X9A60 #define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0X9A49 #define PCI_DEVICE_ID_INTEL_TGL_GT2 0XFF20 @@ -3280,7 +3291,9 @@ #define PCI_DEVICE_ID_INTEL_CML_ULT_6_2 0x9B51 #define PCI_DEVICE_ID_INTEL_CML_ULX 0x9B60 #define PCI_DEVICE_ID_INTEL_CML_S 0x9B55 -#define PCI_DEVICE_ID_INTEL_CML_S_10_2 0x9B35 +#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2 0x9B53 +#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2 0x9B35 +#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2 0x9B43 #define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 #define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 3d46916..8d82385 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -45,8 +45,10 @@ { CPUID_COFFEELAKE_R0, "Coffeelake R0" }, { CPUID_COMETLAKE_U_A0, "Cometlake-U A0 (6+2)" }, { CPUID_COMETLAKE_U_K0_S0, "Cometlake-U K0/S0 (6+2)/(4+2)" }, - { CPUID_COMETLAKE_H_S_6_2_P0, "Cometlake-H/S P0 (6+2)" }, + { CPUID_COMETLAKE_H_S_6_2_G0, "Cometlake-H/S G0 (6+2)" }, + { CPUID_COMETLAKE_H_S_6_2_G1, "Cometlake-H/S G1 (6+2)" }, { CPUID_COMETLAKE_H_S_10_2_P0, "Cometlake-H/S P0 (10+2)" }, + { CPUID_COMETLAKE_H_S_10_2_Q0_P1, "Cometlake-H/S Q0/P1 (10+2)" }, };
static struct { @@ -77,7 +79,9 @@ { PCI_DEVICE_ID_INTEL_CML_ULT_6_2, "CometLake-U (6+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULX, "CometLake-ULX (4+2)" }, { PCI_DEVICE_ID_INTEL_CML_S, "CometLake-S (6+2)" }, - { PCI_DEVICE_ID_INTEL_CML_S_10_2, "CometLake-S (10+2)" }, + { PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2, "CometLake-S G0/G1/P0/P1 (6+2)" }, + { PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2, "CometLake-S P0/P1 (8+2)" }, + { PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2, "CometLake-S P0/P1 (10+2)" }, { PCI_DEVICE_ID_INTEL_CML_H, "CometLake-H (6+2)" }, { PCI_DEVICE_ID_INTEL_CML_H_8_2, "CometLake-H (8+2)" }, }; @@ -104,6 +108,13 @@ { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, "Cometlake-U Premium" }, { PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC, "Cometlake-U Base" }, { PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC, "Cometlake-Y Super" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_HM470, "Cometlake-H HM470" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_WM490, "Cometlake-H WM490" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_QM480, "Cometlake-H QM480" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_W480, "Cometlake-H W480" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_H470, "Cometlake-H H470" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_Z490, "Cometlake-H Z490" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_Q470, "Cometlake-H Q470" }, };
static struct { @@ -143,10 +154,15 @@ { PCI_DEVICE_ID_INTEL_CML_GT1_S_2, "CometLake S GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_S_1, "CometLake S GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT2_S_2, "CometLake S GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_S_G0, "CometLake S GT2 G0" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_S_P0, "CometLake S GT2 P0" }, { PCI_DEVICE_ID_INTEL_CML_GT1_H_1, "CometLake H GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT1_H_2, "CometLake H GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_H_1, "CometLake H GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT2_H_2, "CometLake H GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_H_R0, "CometLake H GT2 R0" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_H_R1, "CometLake H GT2 R1" }, + };
static uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index a7fcd94..c4eb884 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -83,7 +83,8 @@ case 0x02: /* CML-LP */ pch_series = PCH_LP; break; - case 0xA3: + case 0xA3: /* CFL-H */ + case 0x06: /* CML-H */ pch_series = PCH_H; break; default: diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index df571ba..721e42c 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -82,8 +82,10 @@ { X86_VENDOR_INTEL, CPUID_ICELAKE_B0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_A0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_K0_S0 }, - { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_P0 }, + { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_G0 }, + { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_G1 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P0 }, + { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0_P1 }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 }, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index e547538..aaf1793 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -49,8 +49,10 @@ #define CPUID_ICELAKE_B0 0x706e1 #define CPUID_COMETLAKE_U_A0 0xa0660 #define CPUID_COMETLAKE_U_K0_S0 0xa0661 -#define CPUID_COMETLAKE_H_S_6_2_P0 0xa0650 +#define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 +#define CPUID_COMETLAKE_H_S_6_2_G1 0xa0653 #define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 +#define CPUID_COMETLAKE_H_S_10_2_Q0_P1 0xa0654 #define CPUID_TIGERLAKE_A0 0x806c0
/* diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 7ad565d..3f57169 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -359,7 +359,9 @@ PCI_DEVICE_ID_INTEL_CML_ULT_6_2, PCI_DEVICE_ID_INTEL_CML_ULX, PCI_DEVICE_ID_INTEL_CML_S, - PCI_DEVICE_ID_INTEL_CML_S_10_2, + PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2, + PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2, + PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2, PCI_DEVICE_ID_INTEL_CML_H, PCI_DEVICE_ID_INTEL_CML_H_8_2, PCI_DEVICE_ID_INTEL_TGL_ID_U,
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36684
to look at the new patch set (#2).
Change subject: src/soc/intel: Add Cometlake-S and CMP-H skus ......................................................................
src/soc/intel: Add Cometlake-S and CMP-H skus
This patch adds some sku support for CML-S CPU and CMP-H chips. According to doc #605546: CML-S (6+2) G0: A0650h CML-S (6+2) G1: A0653h CML-S (10+2) P0: A0651h CML-S (10+2) Q0/P1: A0654h
CMP-H HM470: 068Dh CMP-H WM490: 068Eh CMP-H QM480: 068Ch CMP-H H470: 0684h CMP-H Z490: 0685h CMP-H Q470: 0687h
TEST=Boot with CML-S (6+2) G1 + CMP-H WM490 and IDs are recognized
Change-Id: I6bda09070ec330033eff95329448ace57e87144f Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/systemagent/systemagent.c 6 files changed, 43 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/36684/2
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36684 )
Change subject: src/soc/intel: Add Cometlake-S and CMP-H skus ......................................................................
Patch Set 2:
(1 comment)
Is this product launched? Why are there no microcode updates available?
https://review.coreboot.org/c/coreboot/+/36684/2/src/soc/intel/cannonlake/bo... File src/soc/intel/cannonlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/36684/2/src/soc/intel/cannonlake/bo... PS2, Line 48: { CPUID_COMETLAKE_H_S_6_2_P0, "Cometlake-H/S P0 (6+2)" Why is this one gone?
Gaggery Tsai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36684 )
Change subject: src/soc/intel: Add Cometlake-S and CMP-H skus ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36684/2/src/soc/intel/cannonlake/bo... File src/soc/intel/cannonlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/36684/2/src/soc/intel/cannonlake/bo... PS2, Line 48: { CPUID_COMETLAKE_H_S_6_2_P0, "Cometlake-H/S P0 (6+2)"
Why is this one gone?
I think the original P0 info is incorrect or mapping to older version. With the latest doc #605546, CPU ID 0xA0650 is G0. P0 is 0xA0651 and there is no (6+2) sku for P0.
Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Lean Sheng Tan, Rizwan Qureshi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36684
to look at the new patch set (#3).
Change subject: src/soc/intel: Add Cometlake-S and CMP-H skus ......................................................................
src/soc/intel: Add Cometlake-S and CMP-H skus
This patch adds some sku support for CML-S CPU and CMP-H chips. According to doc #605546: CML-S (6+2) G0: A0650h CML-S (6+2) G1: A0653h CML-S (10+2, 8+2) P0: A0651h CML-S (6+2, 10+2) Q0/P1: A0654h
CMP-H HM470: 068Dh CMP-H WM490: 068Eh CMP-H QM480: 068Ch CMP-H H470: 0684h CMP-H Z490: 0685h CMP-H Q470: 0687h
TEST=Boot with CML-S (6+2) G1 + CMP-H WM490 and IDs are recognized
Change-Id: I6bda09070ec330033eff95329448ace57e87144f Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/systemagent/systemagent.c 6 files changed, 43 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/36684/3
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36684 )
Change subject: src/soc/intel: Add Cometlake-S and CMP-H skus ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/36684/3/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/36684/3/src/include/device/pci_ids.... PS3, Line 3295: one less tab looks better?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36684 )
Change subject: src/soc/intel: Add Cometlake-S and CMP-H skus ......................................................................
Patch Set 3: Code-Review+1
Hello Patrick Rudolph, Angel Pons, Subrata Banik, Balaji Manigandan, Lean Sheng Tan, Rizwan Qureshi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36684
to look at the new patch set (#4).
Change subject: src/soc/intel: Add Cometlake-S and CMP-H skus ......................................................................
src/soc/intel: Add Cometlake-S and CMP-H skus
This patch adds some sku support for CML-S CPU and CMP-H chips. According to doc #605546: CML-S (6+2) G0: A0650h CML-S (6+2) G1: A0653h CML-S (10+2, 8+2) P0: A0651h CML-S (6+2, 10+2) Q0/P1: A0654h
CMP-H HM470: 068Dh CMP-H WM490: 068Eh CMP-H QM480: 068Ch CMP-H H470: 0684h CMP-H Z490: 0685h CMP-H Q470: 0687h
TEST=Boot with CML-S (6+2) G1 + CMP-H WM490 and IDs are recognized
Change-Id: I6bda09070ec330033eff95329448ace57e87144f Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/systemagent/systemagent.c 6 files changed, 48 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/36684/4
Hello Patrick Rudolph, Angel Pons, Subrata Banik, Balaji Manigandan, Lean Sheng Tan, Rizwan Qureshi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36684
to look at the new patch set (#5).
Change subject: src/soc/intel: Add Cometlake-S and CMP-H skus ......................................................................
src/soc/intel: Add Cometlake-S and CMP-H skus
This patch adds some sku support for CML-S CPU and CMP-H chips. According to doc #605546: CML-S (6+2) G0: A0650h CML-S (6+2) G1: A0653h CML-S (10+2, 8+2) P0: A0651h CML-S (6+2, 10+2) Q0/P1: A0654h
CMP-H HM470: 068Dh CMP-H WM490: 068Eh CMP-H QM480: 068Ch CMP-H H470: 0684h CMP-H Z490: 0685h CMP-H Q470: 0687h
TEST=Boot with CML-S (6+2) G1 + CMP-H WM490 and IDs are recognized
Change-Id: I6bda09070ec330033eff95329448ace57e87144f Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/systemagent/systemagent.c 6 files changed, 48 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/36684/5
Gaggery Tsai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36684 )
Change subject: src/soc/intel: Add Cometlake-S and CMP-H skus ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36684/3/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/36684/3/src/include/device/pci_ids.... PS3, Line 3295:
one less tab looks better?
done.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36684 )
Change subject: src/soc/intel: Add Cometlake-S and CMP-H skus ......................................................................
Patch Set 5: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36684 )
Change subject: src/soc/intel: Add Cometlake-S and CMP-H skus ......................................................................
Patch Set 5: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/36684/3/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/36684/3/src/include/device/pci_ids.... PS3, Line 3295:
done.
Done
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36684 )
Change subject: src/soc/intel: Add Cometlake-S and CMP-H skus ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36684/2/src/soc/intel/cannonlake/bo... File src/soc/intel/cannonlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/36684/2/src/soc/intel/cannonlake/bo... PS2, Line 48: { CPUID_COMETLAKE_H_S_6_2_P0, "Cometlake-H/S P0 (6+2)"
I think the original P0 info is incorrect or mapping to older version. […]
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36684 )
Change subject: src/soc/intel: Add Cometlake-S and CMP-H skus ......................................................................
src/soc/intel: Add Cometlake-S and CMP-H skus
This patch adds some sku support for CML-S CPU and CMP-H chips. According to doc #605546: CML-S (6+2) G0: A0650h CML-S (6+2) G1: A0653h CML-S (10+2, 8+2) P0: A0651h CML-S (6+2, 10+2) Q0/P1: A0654h
CMP-H HM470: 068Dh CMP-H WM490: 068Eh CMP-H QM480: 068Ch CMP-H H470: 0684h CMP-H Z490: 0685h CMP-H Q470: 0687h
TEST=Boot with CML-S (6+2) G1 + CMP-H WM490 and IDs are recognized
Change-Id: I6bda09070ec330033eff95329448ace57e87144f Signed-off-by: Gaggery Tsai gaggery.tsai@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36684 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subrata.banik@intel.com Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/systemagent/systemagent.c 6 files changed, 48 insertions(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 0f96737..b75e596 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2769,6 +2769,14 @@ #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284 #define PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC 0x0285 #define PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC 0x0286 +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_HM470 0x068D +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_WM490 0x068E +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_QM480 0x068C +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_W480 0x0697 +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_H470 0x0684 +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_Z490 0x0685 +#define PCI_DEVICE_ID_INTEL_CMP_H_LPC_Q470 0x0687 +#define PCI_DEVICE_ID_INTEL_TGL_ESPI 0xA083 #define PCI_DEVICE_ID_INTEL_TGP_ESPI_0 0xA080 #define PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI 0xA081 #define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI 0xA082 @@ -3262,6 +3270,14 @@ #define PCI_DEVICE_ID_INTEL_CML_GT1_H_2 0x9B22 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_1 0x9B44 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_2 0x9B42 +#define PCI_DEVICE_ID_INTEL_CML_GT2_S_G0 0x9BC8 +#define PCI_DEVICE_ID_INTEL_CML_GT2_S_P0 0x9BC5 +#define PCI_DEVICE_ID_INTEL_CML_GT2_H_R0 0x3E9B +#define PCI_DEVICE_ID_INTEL_CML_GT2_H_R1 0x9BC4 +#define PCI_DEVICE_ID_INTEL_TGL_GT1 0X9A60 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0X9A49 +#define PCI_DEVICE_ID_INTEL_TGL_GT2 0XFF20 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0X9A40 #define PCI_DEVICE_ID_INTEL_TGL_GT0 0x9A7F #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT 0x9A49 #define PCI_DEVICE_ID_INTEL_TGL_GT3_ULT 0x9A52 @@ -3313,7 +3329,9 @@ #define PCI_DEVICE_ID_INTEL_CML_ULT_6_2 0x9B51 #define PCI_DEVICE_ID_INTEL_CML_ULX 0x9B60 #define PCI_DEVICE_ID_INTEL_CML_S 0x9B55 -#define PCI_DEVICE_ID_INTEL_CML_S_10_2 0x9B35 +#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2 0x9B53 +#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2 0x9B35 +#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2 0x9B43 #define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 #define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 3d46916..8d82385 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -45,8 +45,10 @@ { CPUID_COFFEELAKE_R0, "Coffeelake R0" }, { CPUID_COMETLAKE_U_A0, "Cometlake-U A0 (6+2)" }, { CPUID_COMETLAKE_U_K0_S0, "Cometlake-U K0/S0 (6+2)/(4+2)" }, - { CPUID_COMETLAKE_H_S_6_2_P0, "Cometlake-H/S P0 (6+2)" }, + { CPUID_COMETLAKE_H_S_6_2_G0, "Cometlake-H/S G0 (6+2)" }, + { CPUID_COMETLAKE_H_S_6_2_G1, "Cometlake-H/S G1 (6+2)" }, { CPUID_COMETLAKE_H_S_10_2_P0, "Cometlake-H/S P0 (10+2)" }, + { CPUID_COMETLAKE_H_S_10_2_Q0_P1, "Cometlake-H/S Q0/P1 (10+2)" }, };
static struct { @@ -77,7 +79,9 @@ { PCI_DEVICE_ID_INTEL_CML_ULT_6_2, "CometLake-U (6+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULX, "CometLake-ULX (4+2)" }, { PCI_DEVICE_ID_INTEL_CML_S, "CometLake-S (6+2)" }, - { PCI_DEVICE_ID_INTEL_CML_S_10_2, "CometLake-S (10+2)" }, + { PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2, "CometLake-S G0/G1/P0/P1 (6+2)" }, + { PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2, "CometLake-S P0/P1 (8+2)" }, + { PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2, "CometLake-S P0/P1 (10+2)" }, { PCI_DEVICE_ID_INTEL_CML_H, "CometLake-H (6+2)" }, { PCI_DEVICE_ID_INTEL_CML_H_8_2, "CometLake-H (8+2)" }, }; @@ -104,6 +108,13 @@ { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, "Cometlake-U Premium" }, { PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC, "Cometlake-U Base" }, { PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC, "Cometlake-Y Super" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_HM470, "Cometlake-H HM470" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_WM490, "Cometlake-H WM490" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_QM480, "Cometlake-H QM480" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_W480, "Cometlake-H W480" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_H470, "Cometlake-H H470" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_Z490, "Cometlake-H Z490" }, + { PCI_DEVICE_ID_INTEL_CMP_H_LPC_Q470, "Cometlake-H Q470" }, };
static struct { @@ -143,10 +154,15 @@ { PCI_DEVICE_ID_INTEL_CML_GT1_S_2, "CometLake S GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_S_1, "CometLake S GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT2_S_2, "CometLake S GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_S_G0, "CometLake S GT2 G0" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_S_P0, "CometLake S GT2 P0" }, { PCI_DEVICE_ID_INTEL_CML_GT1_H_1, "CometLake H GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT1_H_2, "CometLake H GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_H_1, "CometLake H GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT2_H_2, "CometLake H GT2" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_H_R0, "CometLake H GT2 R0" }, + { PCI_DEVICE_ID_INTEL_CML_GT2_H_R1, "CometLake H GT2 R1" }, + };
static uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index a7fcd94..c4eb884 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -83,7 +83,8 @@ case 0x02: /* CML-LP */ pch_series = PCH_LP; break; - case 0xA3: + case 0xA3: /* CFL-H */ + case 0x06: /* CML-H */ pch_series = PCH_H; break; default: diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index df571ba..721e42c 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -82,8 +82,10 @@ { X86_VENDOR_INTEL, CPUID_ICELAKE_B0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_A0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_K0_S0 }, - { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_P0 }, + { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_G0 }, + { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_G1 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P0 }, + { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0_P1 }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 }, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index e547538..aaf1793 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -49,8 +49,10 @@ #define CPUID_ICELAKE_B0 0x706e1 #define CPUID_COMETLAKE_U_A0 0xa0660 #define CPUID_COMETLAKE_U_K0_S0 0xa0661 -#define CPUID_COMETLAKE_H_S_6_2_P0 0xa0650 +#define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 +#define CPUID_COMETLAKE_H_S_6_2_G1 0xa0653 #define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 +#define CPUID_COMETLAKE_H_S_10_2_Q0_P1 0xa0654 #define CPUID_TIGERLAKE_A0 0x806c0
/* diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 5f7d5af..b365706 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -359,7 +359,9 @@ PCI_DEVICE_ID_INTEL_CML_ULT_6_2, PCI_DEVICE_ID_INTEL_CML_ULX, PCI_DEVICE_ID_INTEL_CML_S, - PCI_DEVICE_ID_INTEL_CML_S_10_2, + PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2, + PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2, + PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2, PCI_DEVICE_ID_INTEL_CML_H, PCI_DEVICE_ID_INTEL_CML_H_8_2, PCI_DEVICE_ID_INTEL_TGL_ID_U,