EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
mb/google/brya: Add memory DQ map
Add memory DQ map based on latest schematic.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I94102240b13d2b95e0295f41bc2c0ba078faf242 --- M src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/brya/variants/baseboard/memory.c 2 files changed, 85 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/48446/1
diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h index 6f41718..acce85b 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h @@ -11,4 +11,10 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK
+/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_E11 +#define GPIO_MEM_CONFIG_1 GPP_E2 +#define GPIO_MEM_CONFIG_2 GPP_E1 +#define GPIO_MEM_CONFIG_3 GPP_E12 + #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/brya/variants/baseboard/memory.c b/src/mainboard/google/brya/variants/baseboard/memory.c new file mode 100644 index 0000000..dafeb3b --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/memory.c @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +static const struct lpddr4x_cfg baseboard_lpddr4x_memcfg = { + /* DQ CPU<>DRAM map */ + .dq_map = { + [0] = { + { 0, 1, 2, 3, 4, 5, 6, 7, }, /* DDR0_DQ0[7:0] */ + { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 7, 2, 6, 3, 5, 1, 4, 0, }, /* DDR1_DQ0[7:0] */ + { 10, 8, 9, 11, 15, 12, 14, 13, }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + { 15, 14, 8, 9, 10, 12, 11, 13, }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR4_DQ0[7:0] */ + { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + { 13, 12, 11, 10, 14, 15, 9, 8, }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + { 15, 14, 13, 12, 8, 9, 10, 11, }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + { 15, 14, 9, 8, 12, 10, 11, 13, }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg baseboard_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &baseboard_lpddr4x_memcfg +}; + +const struct ddr_memory_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +}
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 1:
I checked the schematic, DQ map is same as Volteer 😊
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... PS1, Line 7: lpddr4x_cfg I think there is some work required in soc/intel/alderlake to organize the meminit code for ADL similar to TGL. Also bug here: b/172978729
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... PS1, Line 7: lpddr4x_cfg
I think there is some work required in soc/intel/alderlake to organize the meminit code for ADL simi […]
I can't access b/172978729. Would you like to add me into cc list?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... PS1, Line 7: lpddr4x_cfg
I can't access b/172978729. […]
Can you please try again? I just added group alias to it.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... PS1, Line 7: lpddr4x_cfg
Can you please try again? I just added group alias to it.
Thanks, I'll follow up this.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... PS1, Line 7: lpddr4x_cfg
Thanks, I'll follow up this.
If they don't have intend to follow TGL, I can follow the adlrvp to change this.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... PS1, Line 7: lpddr4x_cfg
If they don't have intend to follow TGL, I can follow the adlrvp to change this.
I had talked to Subrata about keeping this similar to TGL and hence the bug. If you have cycles, I would recommend taking the bug up since it keeps things simpler in the mainboard.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... PS1, Line 7: lpddr4x_cfg
If they don't have intend to follow TGL, I can follow the adlrvp to change this.
these mappings look correct to me
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... PS1, Line 7: lpddr4x_cfg
these mappings look correct to me
Tim, would you like to raise the issue for this? I'm fine with both way. I'll change to adlrvp way for our bring up, then we can change back if Intel ready for it.
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48446
to look at the new patch set (#2).
Change subject: mb/google/brya: Add memory DQ map ......................................................................
mb/google/brya: Add memory DQ map
Add memory DQ map based on latest schematic.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I94102240b13d2b95e0295f41bc2c0ba078faf242 --- M src/mainboard/google/brya/romstage.c M src/mainboard/google/brya/variants/baseboard/Makefile.inc M src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/brya/variants/baseboard/memory.c 5 files changed, 69 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/48446/2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... PS1, Line 7: lpddr4x_cfg
Tim, would you like to raise the issue for this? I'm fine with both way. […]
b/172978729 is the raised issue. I would highly recommend fixing the ADL code to accept input in this format as it makes things really easy to understand and compare to schematics.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... PS1, Line 7: lpddr4x_cfg
b/172978729 is the raised issue. […]
Any progress here?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... PS1, Line 7: lpddr4x_cfg
Any progress here?
see CB:48860
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/48446/1/src/mainboard/google/brya/v... PS1, Line 7: lpddr4x_cfg
see CB:48860
okay, I can change back after your done. SG!
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48446
to look at the new patch set (#3).
Change subject: mb/google/brya: Add memory DQ map ......................................................................
mb/google/brya: Add memory DQ map
Add memory DQ map based on latest schematic.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I94102240b13d2b95e0295f41bc2c0ba078faf242 --- M src/mainboard/google/brya/romstage.c M src/mainboard/google/brya/variants/baseboard/Makefile.inc M src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/brya/variants/baseboard/memory.c 5 files changed, 102 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/48446/3
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/48446/comment/a85931e8_c304bfa2 PS1, Line 7: lpddr4x_cfg
okay, I can change back after your done. […]
Done
Attention is currently required from: Furquan Shaikh, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 3: Code-Review+2
Attention is currently required from: EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 5: Code-Review+2
(2 comments)
File src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h:
https://review.coreboot.org/c/coreboot/+/48446/comment/91fbfa15_4dc55be6 PS5, Line 14: /* Memory configuration board straps */ Honestly, I think we don't need these GPIO_* macros here. These are used in just one place and if any variant wants to change this, they need to add #undef #define for each of the pins. I think let's drop it for now and any variant that wants to use these differently can provide a strong definition of `variant_memory_sku()`.
https://review.coreboot.org/c/coreboot/+/48446/comment/5a3017e9_c2a24ffe PS5, Line 20: GPIO_MEM_CH_SEL Same here. This is used in just one place. Let's just drop it from here for now.
Attention is currently required from: EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48446
to look at the new patch set (#6).
Change subject: mb/google/brya: Add memory DQ map ......................................................................
mb/google/brya: Add memory DQ map
Add memory DQ map based on latest schematic.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I94102240b13d2b95e0295f41bc2c0ba078faf242 --- M src/mainboard/google/brya/romstage.c M src/mainboard/google/brya/variants/baseboard/Makefile.inc M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/brya/variants/baseboard/memory.c 4 files changed, 108 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/48446/6
Attention is currently required from: EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 6:
(3 comments)
File src/mainboard/google/brya/romstage.c:
https://review.coreboot.org/c/coreboot/+/48446/comment/84967a17_4e8ab5f4 PS6, Line 12: ; ()
File src/mainboard/google/brya/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/48446/comment/b3e6ebb7_47f2eced PS6, Line 68: /* Memory configuration board straps */ : #define GPIO_MEM_CONFIG_0 GPP_E11 : #define GPIO_MEM_CONFIG_1 GPP_E2 : #define GPIO_MEM_CONFIG_2 GPP_E1 : #define GPIO_MEM_CONFIG_3 GPP_E12 I think we can just drop the macros completely.
https://review.coreboot.org/c/coreboot/+/48446/comment/31e54899_b0d0ba1a PS6, Line 86: #define GPIO_MEM_CH_SEL GPP_E13 Not really required. You can use GPP_E13 directly.
Attention is currently required from: EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48446
to look at the new patch set (#7).
Change subject: mb/google/brya: Add memory DQ map ......................................................................
mb/google/brya: Add memory DQ map
Add memory DQ map based on latest schematic.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I94102240b13d2b95e0295f41bc2c0ba078faf242 --- M src/mainboard/google/brya/romstage.c M src/mainboard/google/brya/variants/baseboard/Makefile.inc M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/brya/variants/baseboard/memory.c 4 files changed, 108 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/48446/7
Attention is currently required from: Furquan Shaikh. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 7:
(5 comments)
File src/mainboard/google/brya/romstage.c:
https://review.coreboot.org/c/coreboot/+/48446/comment/f0580426_a954f41b PS6, Line 12: ;
()
Done
File src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h:
https://review.coreboot.org/c/coreboot/+/48446/comment/85332b5c_a17165b0 PS5, Line 14: /* Memory configuration board straps */
Honestly, I think we don't need these GPIO_* macros here. […]
Done
https://review.coreboot.org/c/coreboot/+/48446/comment/27c51955_98331113 PS5, Line 20: GPIO_MEM_CH_SEL
Same here. This is used in just one place. Let's just drop it from here for now.
Done
File src/mainboard/google/brya/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/48446/comment/c43b3269_5e44fc36 PS6, Line 68: /* Memory configuration board straps */ : #define GPIO_MEM_CONFIG_0 GPP_E11 : #define GPIO_MEM_CONFIG_1 GPP_E2 : #define GPIO_MEM_CONFIG_2 GPP_E1 : #define GPIO_MEM_CONFIG_3 GPP_E12
I think we can just drop the macros completely.
Done
https://review.coreboot.org/c/coreboot/+/48446/comment/adde91bb_04131780 PS6, Line 86: #define GPIO_MEM_CH_SEL GPP_E13
Not really required. You can use GPP_E13 directly.
Done
Attention is currently required from: EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
Patch Set 7: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48446 )
Change subject: mb/google/brya: Add memory DQ map ......................................................................
mb/google/brya: Add memory DQ map
Add memory DQ map based on latest schematic.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I94102240b13d2b95e0295f41bc2c0ba078faf242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48446 Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/brya/romstage.c M src/mainboard/google/brya/variants/baseboard/Makefile.inc M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/brya/variants/baseboard/memory.c 4 files changed, 108 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/brya/romstage.c b/src/mainboard/google/brya/romstage.c index 341df15..475bf61 100644 --- a/src/mainboard/google/brya/romstage.c +++ b/src/mainboard/google/brya/romstage.c @@ -1,9 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <baseboard/gpio.h> +#include <baseboard/variants.h> #include <fsp/api.h> +#include <gpio.h> #include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *memupd) { - /* ToDo : Fill FSP-M memory params */ + const struct mb_cfg *mem_config = variant_memory_params(); + bool half_populated = variant_is_half_populated(); + + const struct mem_spd spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, + .cbfs_index = variant_memory_sku(), + }; + + memcfg_init(&memupd->FspmConfig, mem_config, &spd_info, half_populated); } diff --git a/src/mainboard/google/brya/variants/baseboard/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/Makefile.inc index 9fb63f5..1d38b77 100644 --- a/src/mainboard/google/brya/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/brya/variants/baseboard/Makefile.inc @@ -1,3 +1,5 @@ bootblock-y += gpio.c
+romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index 663306c..fb105e8 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -4,6 +4,7 @@ #define __BASEBOARD_VARIANTS_H__
#include <soc/gpio.h> +#include <soc/meminit.h> #include <stdint.h>
/* The next set of functions return the gpio table and fill in the number of entries for @@ -14,4 +15,8 @@ const struct pad_config *variant_early_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num);
+const struct mb_cfg *variant_memory_params(void); +int variant_memory_sku(void); +bool variant_is_half_populated(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/brya/variants/baseboard/memory.c b/src/mainboard/google/brya/variants/baseboard/memory.c new file mode 100644 index 0000000..b0c1509 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/memory.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP4X, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 0, 1, 2, 3, 4, 5, 6, 7, }, + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, + }, + .ddr1 = { + .dq0 = { 7, 2, 6, 3, 5, 1, 4, 0, }, + .dq1 = { 10, 8, 9, 11, 15, 12, 14, 13, }, + }, + .ddr2 = { + .dq0 = { 3, 2, 1, 0, 4, 5, 6, 7, }, + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, + }, + .ddr3 = { + .dq0 = { 7, 0, 1, 6, 5, 4, 2, 3, }, + .dq1 = { 15, 14, 8, 9, 10, 12, 11, 13, }, + }, + .ddr4 = { + .dq0 = { 3, 2, 1, 0, 4, 5, 6, 7, }, + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, + }, + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, + .dq1 = { 13, 12, 11, 10, 14, 15, 9, 8, }, + }, + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6, }, + .dq1 = { 15, 14, 13, 12, 8, 9, 10, 11, }, + }, + .ddr7 = { + .dq0 = { 3, 4, 2, 5, 1, 0, 7, 6, }, + .dq1 = { 15, 14, 9, 8, 12, 10, 11, 13, }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E11 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E1 + * GPIO_MEM_CONFIG_3 GPP_E12 + */ + gpio_t spd_gpios[] = { + GPP_E11, + GPP_E2, + GPP_E1, + GPP_E12, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool __weak variant_is_half_populated(void) +{ + /* GPIO_MEM_CH_SEL GPP_E13 */ + return gpio_get(GPP_E13); +}
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