Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/voteer: configure L1Substate for PCIe ......................................................................
mb/google/voteer: configure L1Substate for PCIe
Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround.
BUG=none BRANCH=none TEST= boot to OS and check warm reboot with NVMe
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a --- M src/mainboard/google/volteer/variants/ripto/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/39413/1
diff --git a/src/mainboard/google/volteer/variants/ripto/overridetree.cb b/src/mainboard/google/volteer/variants/ripto/overridetree.cb index 32204c5..58cedb5 100644 --- a/src/mainboard/google/volteer/variants/ripto/overridetree.cb +++ b/src/mainboard/google/volteer/variants/ripto/overridetree.cb @@ -1,5 +1,10 @@ chip soc/intel/tigerlake
+ # NVMe warm reboot workaround + # Limit L1.1(value:2) for RP9, RP11 + register "PcieRpL1Substates[8]" = "2" + register "PcieRpL1Substates[10]" = "2" + device domain 0 on end
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/voteer: configure L1Substate for PCIe ......................................................................
Patch Set 1: Code-Review+1
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/voteer: configure L1Substate for PCIe ......................................................................
Patch Set 1:
Patch Set 1: Code-Review+1
would it make sense to redo this as a cherry pick of the original patch?
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/voteer: configure L1Substate for PCIe ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39413/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/ripto/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39413/1/src/mainboard/google/voltee... PS1, Line 5: PcieRpL1Substates I don't have this patch / these changes in place, but can boot my Ripto from NVME successfully. Why is that?
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/voteer: configure L1Substate for PCIe ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39413/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/ripto/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39413/1/src/mainboard/google/voltee... PS1, Line 5: PcieRpL1Substates
I don't have this patch / these changes in place, but can boot my Ripto from NVME successfully. […]
cold boot is ok but warm reboot has issue with this change and ES1
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/voteer: configure L1Substate for PCIe ......................................................................
Patch Set 1: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/voteer: configure L1Substate for PCIe ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39413/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39413/1//COMMIT_MSG@9 PS1, Line 9: ES1 NVMe warm reboot workaround What is the bug?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/voteer: configure L1Substate for PCIe ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39413/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/ripto/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39413/1/src/mainboard/google/voltee... PS1, Line 5: PcieRpL1Substates
cold boot is ok but warm reboot has issue with this change and ES1
What is the issue?
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Caveh Jalali, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39413
to look at the new patch set (#2).
Change subject: mb/google/voteer: configure L1Substate for PCIe ......................................................................
mb/google/voteer: configure L1Substate for PCIe
Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround.
Reference: #613582 Tiger Lake PCH-LP Sightings Report issue id #1409566330
BUG=none BRANCH=none TEST= boot to OS and check warm reboot with NVMe
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a --- M src/mainboard/google/volteer/variants/ripto/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/39413/2
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/voteer: configure L1Substate for PCIe ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39413/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39413/1//COMMIT_MSG@9 PS1, Line 9: ES1 NVMe warm reboot workaround
What is the bug?
Issue is in 1409566330 in Tiger Lake PCH-LP Sightings Report(613582)
https://review.coreboot.org/c/coreboot/+/39413/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/ripto/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39413/1/src/mainboard/google/voltee... PS1, Line 5: PcieRpL1Substates
What is the issue?
Issue is in 1409566330 in Tiger Lake PCH-LP Sightings Report(613582)
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/voteer: configure L1Substate for PCIe ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39413/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39413/2//COMMIT_MSG@7 PS2, Line 7: voteer typo: vo*l*teer
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Caveh Jalali, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39413
to look at the new patch set (#3).
Change subject: mb/google/volteer: configure L1Substate for PCIe ......................................................................
mb/google/volteer: configure L1Substate for PCIe
Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround.
Reference: #613582 Tiger Lake PCH-LP Sightings Report issue id #1409566330
BUG=none BRANCH=none TEST= boot to OS and check warm reboot with NVMe
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a --- M src/mainboard/google/volteer/variants/ripto/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/39413/3
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/volteer: configure L1Substate for PCIe ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39413/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39413/2//COMMIT_MSG@7 PS2, Line 7: voteer
typo: vo*l*teer
Ack
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/volteer: configure L1Substate for PCIe ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39413/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/ripto/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39413/1/src/mainboard/google/voltee... PS1, Line 5: register "PcieRpL1Substates[8]" = "2" is that an issuetracker bug number? it seems to be invalid on our end.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/volteer: configure L1Substate for PCIe ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39413/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/ripto/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39413/1/src/mainboard/google/voltee... PS1, Line 5: register "PcieRpL1Substates[8]" = "2"
is that an issuetracker bug number? it seems to be invalid on our end.
We don't have partner bug as this issue fixed long time back for ES1. And it'll affect warm reboot with NVMe memory:After warm reboot, NVMe is not detected. Do you want to create partner bug for this and add partner bug info?
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/volteer: configure L1Substate for PCIe ......................................................................
Patch Set 4: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/volteer: configure L1Substate for PCIe ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39413/4/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/ripto/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39413/4/src/mainboard/google/voltee... PS4, Line 4: # Limit L1.1(value:2) for RP9, RP11 Please add a space before the (.
https://review.coreboot.org/c/coreboot/+/39413/4/src/mainboard/google/voltee... PS4, Line 5: register "PcieRpL1Substates[8]" = "2" What is the default value?
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Caveh Jalali, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39413
to look at the new patch set (#5).
Change subject: mb/google/volteer: configure L1Substate for PCIe ......................................................................
mb/google/volteer: configure L1Substate for PCIe
Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround.
Reference: #613582 Tiger Lake PCH-LP Sightings Report issue id #1409566330
BUG=none BRANCH=none TEST= boot to OS and check warm reboot with NVMe
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a --- M src/mainboard/google/volteer/variants/ripto/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/39413/5
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/volteer: configure L1Substate for PCIe ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39413/4/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/ripto/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39413/4/src/mainboard/google/voltee... PS4, Line 4: # Limit L1.1(value:2) for RP9, RP11
Please add a space before the (.
Done
https://review.coreboot.org/c/coreboot/+/39413/4/src/mainboard/google/voltee... PS4, Line 5: register "PcieRpL1Substates[8]" = "2"
What is the default value?
Default value is 0 (FSP default: L1.2)
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/volteer: configure L1Substate for PCIe ......................................................................
Patch Set 5: Code-Review+1
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/volteer: configure L1Substate for PCIe ......................................................................
Patch Set 5: Code-Review+2
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/volteer: configure L1Substate for PCIe ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/volteer: configure L1Substate for PCIe ......................................................................
mb/google/volteer: configure L1Substate for PCIe
Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround.
Reference: #613582 Tiger Lake PCH-LP Sightings Report issue id #1409566330
BUG=none BRANCH=none TEST= boot to OS and check warm reboot with NVMe
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39413 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Reviewed-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/volteer/variants/ripto/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Srinidhi N Kaushik: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/ripto/overridetree.cb b/src/mainboard/google/volteer/variants/ripto/overridetree.cb index 32204c5..162f93b 100644 --- a/src/mainboard/google/volteer/variants/ripto/overridetree.cb +++ b/src/mainboard/google/volteer/variants/ripto/overridetree.cb @@ -1,5 +1,10 @@ chip soc/intel/tigerlake
+ # NVMe warm reboot workaround + # Limit L1.1 (value:2) for RP9, RP11 + register "PcieRpL1Substates[8]" = "2" + register "PcieRpL1Substates[10]" = "2" + device domain 0 on end
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/volteer: configure L1Substate for PCIe ......................................................................
Patch Set 6:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1319 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1318 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1317
Please note: This test is under development and might not be accurate at all!
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39413 )
Change subject: mb/google/volteer: configure L1Substate for PCIe ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39413/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/ripto/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39413/6/src/mainboard/google/voltee... PS6, Line 5: 2 Please use the provided enums in chip.h.
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Caveh Jalali (Code Review)
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Furquan Shaikh (Code Review)
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Nick Vaccaro (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)
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Srinidhi N Kaushik (Code Review)
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Wonkyu Kim (Code Review)