[S] Change in coreboot[main]: soc/amd/common/block/pci: Prevent disabling active bridges

[Patrick Rudolph (Code Review)]

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph.

Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86216?usp=email

to look at the new patch set (#2).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/amd/common/block/pci: Prevent disabling active bridges
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soc/amd/common/block/pci: Prevent disabling active bridges

To avoid PCI resource conflicts always assert and ignore when an
active PPB is marked as disabled. Since FSP doesn't disable or hide PPB,
they must never be marked as disabled in the devicetree.cb.

Change-Id: Ia97098c860aa6cd6b0b59aa7b1c6f7c239e41983
Signed-off-by: Patrick Rudolph 
---
M src/soc/amd/common/block/pci/pcie_gpp.c
1 file changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/86216/2