Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50892 )
Change subject: soc/amd: Move root complex SSDT TOM1/TOM2 generation function
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/acpi/tables.c:
https://review.coreboot.org/c/coreboot/+/50892/comment/980ef651_f57dfde2
PS1, Line 75: */
Ack
i don't think that it's a good idea to delete TOM2, since we'll need that when we want to support PCIe BARs above 4GiB, right? but unrelated to this patch
--
To view, visit
https://review.coreboot.org/c/coreboot/+/50892
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7c8f476a7735fea61a3244b97988e3ead3b42e79
Gerrit-Change-Number: 50892
Gerrit-PatchSet: 1
Gerrit-Owner: Raul Rangel
rrangel@chromium.org
Gerrit-Reviewer: Angel Pons
th3fanbus@gmail.com
Gerrit-Reviewer: Felix Held
felix-coreboot@felixheld.de
Gerrit-Reviewer: Jason Glenesk
jason.glenesk@gmail.com
Gerrit-Reviewer: Marshall Dawson
marshalldawson3rd@gmail.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-Attention: Jason Glenesk
jason.glenesk@gmail.com
Gerrit-Attention: Raul Rangel
rrangel@chromium.org
Gerrit-Attention: Marshall Dawson
marshalldawson3rd@gmail.com
Gerrit-Comment-Date: Fri, 19 Feb 2021 17:58:12 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Raul Rangel
rrangel@chromium.org
Comment-In-Reply-To: Angel Pons
th3fanbus@gmail.com
Gerrit-MessageType: comment