[S] Change in coreboot[main]: cpu/x86/64bit: Back up/restore CR3 on mode switch

[Patrick Rudolph (Code Review)]

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82164?usp=email )

Change subject: cpu/x86/64bit: Back up/restore CR3 on mode switch
......................................................................

cpu/x86/64bit: Back up/restore CR3 on mode switch

Store CR3 on stack and restore it when returning from protected
mode call, since the stage might have set up different page tables
than the default ones linked into all stages.

Tested: intel/archercity still boots to payload in x86_64.

Change-Id: If94a24925994ac9599be24f6454ea28d02ff0c67
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82164
Tested-by: build bot (Jenkins) 
Reviewed-by: Maximilian Brune 
---
M src/cpu/x86/64bit/mode_switch.S
1 file changed, 10 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Maximilian Brune: Looks good to me, approved

diff --git a/src/cpu/x86/64bit/mode_switch.S b/src/cpu/x86/64bit/mode_switch.S
index e5be44a3..a4c58f2 100644
--- a/src/cpu/x86/64bit/mode_switch.S
+++ b/src/cpu/x86/64bit/mode_switch.S
@@ -26,6 +26,10 @@
    /* Store stack pointer */
    mov	%rsp, %rbp

+	/* Backup cr3 to stack */
+	mov	%cr3, %rax
+	push	%rax
+
    /* New IDT to stack */
    pushq	$0
    pushq	$0
@@ -47,7 +51,7 @@
    #include <cpu/x86/64bit/exit32.inc>

/* Load zero IDT. x86_32 FSP doesn't like to find a x86_64 IDT */
-	lidt	-16(%ebp)
+	lidt	-24(%ebp)

/* Fetch function to call */
    movl	12(%esp), %ebx
@@ -56,8 +60,11 @@
    call	*%ebx
    movl	%eax, %ebx

-	/* Preserves ebx */
-	setup_longmode $PM4LE
+	/*
+	 * Back to long mode by using cr3 previously stored on stack.
+	 * Preserves ebx.
+	 */
+	setup_longmode -8(%ebp)

/* Place return value in rax */
    movl	%ebx, %eax