Change in coreboot[master]: soc/mediatek/mt8186: Adjust usage of SRAM L2C - coreboot-gerrit

27 Dec 2021


      Attention is currently required from: Paul Menzel, Yu-Ping Wu.
Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60316 )
Change subject: soc/mediatek/mt8186: Adjust usage of SRAM L2C
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Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60316/comment/5e0dc319_999bb450 
PS4, Line 9: However the BootROM
           : has configured only half of L2/L3 cache as SRAM.
...
No, it's not a bug. […]
Sorry for error type:
because "it's unchangeable" when the SoCs are taped out.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2
Gerrit-Change-Number: 60316
Gerrit-PatchSet: 5
Gerrit-Owner: Rex-BC Chen rex-bc.chen@mediatek.com
Gerrit-Reviewer: Hung-Te Lin hungte@chromium.org
Gerrit-Reviewer: Rex-BC Chen rex-bc.chen@mediatek.com
Gerrit-Reviewer: Yu-Ping Wu yupingso@google.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
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