Change in coreboot[master]: mb/google/dedede: Export EC_IN_RW GPIO to payload

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51001 )

Change subject: mb/google/dedede: Export EC_IN_RW GPIO to payload
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mb/google/dedede: Export EC_IN_RW GPIO to payload

Set up EC_IN_RW GPIO in coreboot.

BUG=b:180686277
TEST=Verified that EC_IN_RW signal is read correctly in depthcharge.

Signed-off-by: Ian Feng 
Change-Id: Ic41012d3d4843dcab0f6dd9c28396cb9d5c49f08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51001
Tested-by: build bot (Jenkins) 
Reviewed-by: Paul Menzel 
Reviewed-by: Daisuke Nojiri 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Karthik Ramasubramanian 
---
M src/mainboard/google/dedede/chromeos.c
M src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h
2 files changed, 4 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Furquan Shaikh: Looks good to me, approved
  Daisuke Nojiri: Looks good to me, but someone else must approve
  Karthik Ramasubramanian: Looks good to me, approved

diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c
index 0b77ebb..fb904cc 100644
--- a/src/mainboard/google/dedede/chromeos.c
+++ b/src/mainboard/google/dedede/chromeos.c
@@ -12,6 +12,7 @@
    	{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
    	{-1, ACTIVE_HIGH, 0, "power"},
    	{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+		{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
    };
    lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h
index 855ab6d..4b72ae3 100644
--- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h
@@ -17,6 +17,9 @@
 /* EC sync irq is GPP_C15_IRQ */
 #define EC_SYNC_IRQ	GPP_C15_IRQ

+/* EC in RW */
+#define GPIO_EC_IN_RW		GPP_C14
+
 /* Memory configuration board straps */
 #define GPIO_MEM_CONFIG_0	GPP_C0
 #define GPIO_MEM_CONFIG_1	GPP_C3