[S] Change in coreboot[main]: nb/intel/sandybridge/raminit: Set MR2 on per DIMM basis

[Patrick Rudolph (Code Review)]

Attention is currently required from: Angel Pons.

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79783?usp=email )

Change subject: nb/intel/sandybridge/raminit: Set MR2 on per DIMM basis
......................................................................

nb/intel/sandybridge/raminit: Set MR2 on per DIMM basis

Improve mixed DIMM configurations by setting MR2 on per DIMM
basis instead of using the common denominator.
Drop now unused variables and bump the MRC_CACHE revision counter.

The same is done on MRC.bin.

Tested on Lenovo X220: Still boots and works fine.

Change-Id: Ia60d1c01b79be2ac18ca6cc90109f817d1624c55
Signed-off-by: Patrick Rudolph 
---
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/raminit_common.h
3 files changed, 5 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/79783/1

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 085292b..f026043 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -200,9 +200,6 @@

memset(ctrl->rankmap, 0, sizeof(ctrl->rankmap));

-	ctrl->extended_temperature_range = 1;
-	ctrl->auto_self_refresh = 1;
-
    FOR_ALL_CHANNELS {
    	ctrl->channel_size_mb[channel] = 0;

@@ -273,10 +270,6 @@
    		if (!dimm->flags.is_ecc)
    			can_use_ecc = false;

-			ctrl->auto_self_refresh &= dimm->flags.asr;
-
-			ctrl->extended_temperature_range &= dimm->flags.ext_temp_refresh;
-
    		ctrl->rankmap[channel] |= ((1 << dimm->ranks) - 1) << (2 * slot);

printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", channel,
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index de24400..16751b9 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -778,15 +778,16 @@
    const u16 pasr = 0;
    const u16 cwl = ctrl->CWL - 5;
    const odtmap odt = get_ODT(ctrl, channel);
+	struct dimm_attr_ddr3_st *const dimm = &ctrl->info.dimm[channel][rank/2];

int srt = 0;
    if (IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ)
-		srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh;
+		srt = dimm->flags.ext_temp_refresh && !dimm->flags.asr;

u16 mr2reg = 0;
    mr2reg |= pasr;
    mr2reg |= cwl << 3;
-	mr2reg |= ctrl->auto_self_refresh << 6;
+	mr2reg |= dimm->flags.asr << 6;
    mr2reg |= srt << 7;
    mr2reg |= (odt.rttwr / 60) << 9;

@@ -795,7 +796,7 @@
    /* Program MR2 shadow */
    u32 reg32 = mchbar_read32(TC_MR2_SHADOW_ch(channel));

-	reg32 &= 3 << 14 | 3 << 6;
+	reg32 &= 1 << (rank / 2 + 14) | 1 << (rank / 2 + 6);

reg32 |= mr2reg & ~(3 << 6);

diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index ee7c525..3303646 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -305,7 +305,7 @@
 /*
  * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed!
  */
-#define MRC_CACHE_VERSION 5
+#define MRC_CACHE_VERSION 6

enum power_down_mode {
    PDM_NONE        = 0,
@@ -410,9 +410,6 @@
    int edge_offset[3];
    int tx_dq_offset[3];

-	int extended_temperature_range;
-	int auto_self_refresh;
-
    int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS];

struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS];