Change in coreboot[master]: soc/intel/apollolake: postcar stage potentially needs the reset code, ...

[Patrick Georgi (Code Review)]

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/29223

Change subject: soc/intel/apollolake: postcar stage potentially needs the reset code, too
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soc/intel/apollolake: postcar stage potentially needs the reset code, too

Also add a test case for that, a config taken from chromiumos with some
references to binaries dropped that aren't in our blobs repo (eg audio
firmware).

Change-Id: I411c0bacefd9345326f26db4909921dddba28237
Signed-off-by: Patrick Georgi 
---
A configs/config.google_reef_cros
M src/soc/intel/apollolake/Makefile.inc
2 files changed, 17 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29223/1

diff --git a/configs/config.google_reef_cros b/configs/config.google_reef_cros
new file mode 100644
index 0000000..82b9b52
--- /dev/null
+++ b/configs/config.google_reef_cros
@@ -0,0 +1,15 @@
+CONFIG_USE_BLOBS=y
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_BOARD_GOOGLE_REEF=y
+CONFIG_CHROMEOS=y
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y
+CONFIG_ELOG_GSMI=y
+CONFIG_ELOG_BOOT_COUNT=y
+CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144
+CONFIG_SPI_FLASH_SMM=y
+# CONFIG_CONSOLE_SERIAL is not set
+CONFIG_CMOS_POST=y
+CONFIG_CMOS_POST_OFFSET=0x70
+CONFIG_CMOS_POST_EXTRA=y
+CONFIG_PAYLOAD_NONE=y
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 632cb99..ede565a 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -72,6 +72,8 @@
 postcar-y += mmap_boot.c
 postcar-y += spi.c
 postcar-y += i2c.c
+postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c
+postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c
 postcar-$(CONFIG_UART_DEBUG) += uart.c

postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S