HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60803 )
Change subject: src: REmove unused <cf9_reset.h> ......................................................................
src: REmove unused <cf9_reset.h>
Found using: diff <(git grep -l '#include <cf9_reset.h>' -- src/) <(git grep -l 'RST_CNT|FULL_RST|RST_CPU|SYS_RST|do_system_reset|do_full_reset|cf9_reset_prepare|system_reset|full_reset' -- src/) |grep "<"
Change-Id: I093d8412e14ce81b462fb9a7ccb3a2a93ae760a6 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/roda/rk886ex/early_init.c M src/northbridge/intel/ironlake/romstage.c M src/security/intel/txt/romstage.c M src/soc/intel/broadwell/romstage.c M src/soc/intel/common/block/acpi/acpi.c 6 files changed, 0 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/60803/1
diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 92d49c1..e2fd2aa 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -2,7 +2,6 @@
#include <bootblock_common.h> #include <stdint.h> -#include <cf9_reset.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/roda/rk886ex/early_init.c b/src/mainboard/roda/rk886ex/early_init.c index 76471eb..ddea82f 100644 --- a/src/mainboard/roda/rk886ex/early_init.c +++ b/src/mainboard/roda/rk886ex/early_init.c @@ -3,7 +3,6 @@ #include <bootblock_common.h> #include <stdint.h> #include <arch/io.h> -#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index 8d3cfd6..5214b53 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -3,7 +3,6 @@ #include <arch/io.h> #include <stdint.h> #include <console/console.h> -#include <cf9_reset.h> #include <device/pci_ops.h> #include <cpu/x86/lapic.h> #include <timestamp.h> diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c index 98308b7..e045c9d 100644 --- a/src/security/intel/txt/romstage.c +++ b/src/security/intel/txt/romstage.c @@ -2,7 +2,6 @@
#include <arch/cpu.h> #include <arch/mmio.h> -#include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/common/common.h> #include <cpu/x86/cr.h> diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index 09a7283..75563cd 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -3,7 +3,6 @@ #include <acpi/acpi.h> #include <arch/romstage.h> #include <cbmem.h> -#include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/haswell/haswell.h> #include <elog.h> diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index b827c58..4493c33 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -5,7 +5,6 @@ #include <arch/cpu.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> -#include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/turbo.h> #include <cpu/intel/msr.h>
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HAOUAS Elyes (Code Review)