Change in coreboot[master]: soc/intel/alderlake: Drop 100ms delay and do not poll Link Active

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51191 )

Change subject: soc/intel/alderlake: Drop 100ms delay and do not poll Link Active
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soc/intel/alderlake: Drop 100ms delay and do not poll Link Active

Drop the 100ms delay in the _PS0 method because kernel already adds this
100ms. This change also drops polling TBT PCIe root ports Link Active
State because this scheme is not applicable for SW CM.

BUG=None
TEST=Built Alderlake coreboot image successfully.

Signed-off-by: John Zhao 
Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51191
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/alderlake/acpi/tcss_pcierp.asl
1 file changed, 0 insertions(+), 14 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
index 3f495be..07d024a 100644
--- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
@@ -140,18 +140,6 @@
    	Local1 = L23R
    }
    STAT = 0x1
-
-	/* Wait for LA = 1 */
-	Local0 = 0
-	Local1 = LASX
-	While (Local1 == 0) {
-		If (Local0 > 20) {
-			Break
-		}
-		Sleep(5)
-		Local0++
-		Local1 = LASX
-	}
 }

/*
@@ -192,8 +180,6 @@
    If (PMEX == 1) {
    	PMEX = 0  /* Disable Power Management SCI */
    }
-
-	Sleep(100)  /* Wait for 100ms before return to OS starts any OS activities. */
 }

Method (_PS3, 0, Serialized)