[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes

[Keith Hui (Code Review)]

Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin.

Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )

Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
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Patch Set 7:

(2 comments)

Patchset:

PS7: 
Guys, as I wrote on the mailing list, I am getting real close to actually implement the whole thing. Looks like sb/intel/bd82x6x already included the SPI_FLASH Kconfig and related stuff. But how do I use the functions in drivers/spi/spi_flash.c? Or am I better off reinventing the wheel?

File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:

https://review.coreboot.org/c/coreboot/+/85413/comment/1de572e6_5ea66271?usp... :
PS7, Line 104: 0x40
> Unfortunately, as https://ticket.coreboot.org/attachments/487 shows, my board is rev 1. […]

Your photo shows the same six transistors as my boardview, they are:

QSWQ7 QSWQ4 QSWQ6
QSWQ8 QSWQ3 QSWQ5

Pin 3 of Q7 is SEL4.
You can find SEL2 at pin 3 of Q3,
and SEL3 at pin 3 of Q5.

https://ticket.coreboot.org/attachments/489 uploaded with marks showing where to probe instead.

(As you can see, QSWQ8 is not there, but it doesn't matter.)