Change in coreboot[master]: soc/intel/alderlake: Disable VT-d for early silicons

[Meera Ravindranath (Code Review)]

Attention is currently required from: Abhijeet Rao, Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Patrick Rudolph.
Hello Abhijeet Rao, build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/59191

to look at the new patch set (#4).

Change subject: soc/intel/alderlake: Disable VT-d for early silicons
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soc/intel/alderlake: Disable VT-d for early silicons

VT-d needs to disabled for early silicons as it results in a
CPU hard hang.

BUG=b:197177091
Test=Boot brya to OS with no hang

Signed-off-by: Meera Ravindranath 
Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/59191/4