Attention is currently required from: Martin Roth, Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52515 )
Change subject: soc/intel/broadwell: Use Lynx Point IOBP code ......................................................................
soc/intel/broadwell: Use Lynx Point IOBP code
Change-Id: I89832dd6089e1961b4ffdb5661dc98b26a5cb0a2 Signed-off-by: Angel Pons th3fanbus@gmail.com --- D src/soc/intel/broadwell/include/soc/iobp.h M src/soc/intel/broadwell/pch/Makefile.inc M src/soc/intel/broadwell/pch/adsp.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/pch.c M src/soc/intel/broadwell/pch/pcie.c M src/soc/intel/broadwell/pch/sata.c M src/soc/intel/broadwell/pch/serialio.c 8 files changed, 8 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/52515/1
diff --git a/src/soc/intel/broadwell/include/soc/iobp.h b/src/soc/intel/broadwell/include/soc/iobp.h deleted file mode 100644 index e3a6993..0000000 --- a/src/soc/intel/broadwell/include/soc/iobp.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _BROADWELL_IOBP_H_ -#define _BROADWELL_IOBP_H_ - -u32 pch_iobp_read(u32 address); -void pch_iobp_write(u32 address, u32 data); -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -void pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp); - -#endif diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc index b345e8d..414c85c 100644 --- a/src/soc/intel/broadwell/pch/Makefile.inc +++ b/src/soc/intel/broadwell/pch/Makefile.inc @@ -9,8 +9,8 @@ smm-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c ramstage-y += hda.c ramstage-y += ../../../../southbridge/intel/lynxpoint/hda_verb.c -ramstage-y += iobp.c -romstage-y += iobp.c +ramstage-y += ../../../../southbridge/intel/lynxpoint/iobp.c +romstage-y += ../../../../southbridge/intel/lynxpoint/iobp.c ramstage-y += fadt.c ramstage-y += lpc.c ramstage-y += me.c diff --git a/src/soc/intel/broadwell/pch/adsp.c b/src/soc/intel/broadwell/pch/adsp.c index a65ff4b..040bba1 100644 --- a/src/soc/intel/broadwell/pch/adsp.c +++ b/src/soc/intel/broadwell/pch/adsp.c @@ -9,12 +9,12 @@ #include <device/mmio.h> #include <soc/adsp.h> #include <soc/device_nvs.h> -#include <soc/iobp.h> #include <soc/device_nvs.h> #include <soc/pch.h> #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/intel/broadwell/pch/chip.h> +#include <southbridge/intel/lynxpoint/iobp.h>
static void adsp_init(struct device *dev) { diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 170f889..3d617c2 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -11,7 +11,6 @@ #include <arch/ioapic.h> #include <acpi/acpi.h> #include <cpu/x86/smm.h> -#include <soc/iobp.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pch.h> @@ -22,6 +21,7 @@ #include <soc/intel/broadwell/pch/chip.h> #include <acpi/acpigen.h> #include <southbridge/intel/common/rtc.h> +#include <southbridge/intel/lynxpoint/iobp.h> #include <southbridge/intel/lynxpoint/lp_gpio.h>
static void pch_enable_ioapic(struct device *dev) diff --git a/src/soc/intel/broadwell/pch/pch.c b/src/soc/intel/broadwell/pch/pch.c index d4b88f1..20e2431 100644 --- a/src/soc/intel/broadwell/pch/pch.c +++ b/src/soc/intel/broadwell/pch/pch.c @@ -5,13 +5,13 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> -#include <soc/iobp.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/serialio.h> #include <soc/spi.h> +#include <southbridge/intel/lynxpoint/iobp.h>
u8 pch_revision(void) { diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index 26fde0b..28d858f 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -9,11 +9,11 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <soc/lpc.h> -#include <soc/iobp.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/rcba.h> #include <soc/intel/broadwell/pch/chip.h> +#include <southbridge/intel/lynxpoint/iobp.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> #include <delay.h>
diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c index 82760ab..b8ef527 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/soc/intel/broadwell/pch/sata.c @@ -7,11 +7,11 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <delay.h> -#include <soc/iobp.h> #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/sata.h> #include <soc/intel/broadwell/pch/chip.h> +#include <southbridge/intel/lynxpoint/iobp.h>
static inline u32 sir_read(struct device *dev, int idx) { diff --git a/src/soc/intel/broadwell/pch/serialio.c b/src/soc/intel/broadwell/pch/serialio.c index 28f34b7..fa61b91 100644 --- a/src/soc/intel/broadwell/pch/serialio.c +++ b/src/soc/intel/broadwell/pch/serialio.c @@ -7,7 +7,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/iobp.h> #include <soc/device_nvs.h> #include <soc/pci_devs.h> #include <soc/pch.h> @@ -15,6 +14,7 @@ #include <soc/rcba.h> #include <soc/serialio.h> #include <soc/intel/broadwell/pch/chip.h> +#include <southbridge/intel/lynxpoint/iobp.h>
/* Set D3Hot Power State in ACPI mode */ static void serialio_enable_d3hot(struct resource *res)
-
Angel Pons (Code Review)