Change in coreboot[master]: soc/intel/alderlake: Add support to update the FIVR configs

[V Sowmya (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63497 )

Change subject: soc/intel/alderlake: Add support to update the FIVR configs
......................................................................

soc/intel/alderlake: Add support to update the FIVR configs

This patch adds the supports to update the optimal FIVR
configurations for external voltage rails via devicetree.

Signed-off-by: V Sowmya 
Change-Id: I555e5607af15a5f5d83ef74321b1b71f17cca289
---
M src/soc/intel/alderlake/chip.h
1 file changed, 3 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/63497/1

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 2dae9cd..2f48361 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -82,7 +82,7 @@

/*
  * Enable External V1P05/Vnn/VnnSx Rail in: BIT0:S0i1/S0i2,
- * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5
+ * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5, BIT4:S0.
  */
 enum fivr_enable_states {
    FIVR_ENABLE_S0i1_S0i2	= BIT(0),
@@ -90,6 +90,7 @@
    FIVR_ENABLE_S3		= BIT(2),
    FIVR_ENABLE_S4		= BIT(3),
    FIVR_ENABLE_S5		= BIT(4),
+	FIVR_ENABLE_S0		= BIT(5),
 };

/*
@@ -107,7 +108,7 @@
 };

#define FIVR_ENABLE_ALL_SX (FIVR_ENABLE_S0i1_S0i2 | FIVR_ENABLE_S0i3 |	\
-			    FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5)
+			    FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5 | FIVR_ENABLE_S0)
 /*
  * The Max Pkg Cstate
  * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10,