Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38191 )
Change subject: drivers/pc80/rtc: Drop CMOS_POST_EXTRA option ......................................................................
drivers/pc80/rtc: Drop CMOS_POST_EXTRA option
Change-Id: I379a5664776624600ff1c2919bffa77c877d87ab Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M configs/config.google_meep_cros M configs/config.google_reef_cros M src/console/Kconfig M src/drivers/elog/elog.c M src/drivers/pc80/rtc/post.c 5 files changed, 4 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/38191/1
diff --git a/configs/config.google_meep_cros b/configs/config.google_meep_cros index f87b02b..9911614 100644 --- a/configs/config.google_meep_cros +++ b/configs/config.google_meep_cros @@ -14,7 +14,6 @@
# Event Logging CONFIG_CMOS_POST=y -CONFIG_CMOS_POST_EXTRA=y CONFIG_CMOS_POST_OFFSET=0x70 CONFIG_COLLECT_TIMESTAMPS=y CONFIG_ELOG=y diff --git a/configs/config.google_reef_cros b/configs/config.google_reef_cros index 9bbb3b3..6dcda44 100644 --- a/configs/config.google_reef_cros +++ b/configs/config.google_reef_cros @@ -10,5 +10,4 @@ # CONFIG_CONSOLE_SERIAL is not set CONFIG_CMOS_POST=y CONFIG_CMOS_POST_OFFSET=0x70 -CONFIG_CMOS_POST_EXTRA=y CONFIG_PAYLOAD_NONE=y diff --git a/src/console/Kconfig b/src/console/Kconfig index cc18ec3..a5a833a 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -392,14 +392,6 @@ If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value defined in the mainboard option table.
-config CMOS_POST_EXTRA - bool "Store extra logging info into CMOS" - depends on CMOS_POST - default n - help - This will enable extra logging of work that happens between post - codes into CMOS for debug. This uses an additional 8 bytes of CMOS. - config CONSOLE_POST bool "Show POST codes on the debug console" depends on !NO_POST diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 9bd2a61..11cbfba 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -776,7 +776,6 @@
if (ENV_RAMSTAGE || CONFIG(ELOG_PRERAM)) { elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); - /* Always zero with !CMOS_POST_EXTRA. */ if (extra) elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); } diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c index 8308504..38ef241 100644 --- a/src/drivers/pc80/rtc/post.c +++ b/src/drivers/pc80/rtc/post.c @@ -28,13 +28,11 @@ switch (cmos_read(CMOS_POST_BANK_OFFSET)) { case CMOS_POST_BANK_0_MAGIC: *code = cmos_read(CMOS_POST_BANK_1_OFFSET); - if (CONFIG(CMOS_POST_EXTRA)) - *extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); + *extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); break; case CMOS_POST_BANK_1_MAGIC: *code = cmos_read(CMOS_POST_BANK_0_OFFSET); - if (CONFIG(CMOS_POST_EXTRA)) - *extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); + *extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); break; }
@@ -69,10 +67,8 @@ /* Initialize to zero */ cmos_write(0, CMOS_POST_BANK_0_OFFSET); cmos_write(0, CMOS_POST_BANK_1_OFFSET); - if (CONFIG(CMOS_POST_EXTRA)) { - cmos_write32(0, CMOS_POST_BANK_0_EXTRA); - cmos_write32(0, CMOS_POST_BANK_1_EXTRA); - } + cmos_write32(0, CMOS_POST_BANK_0_EXTRA); + cmos_write32(0, CMOS_POST_BANK_1_EXTRA); }
cmos_write(magic, CMOS_POST_BANK_OFFSET); @@ -96,9 +92,6 @@
void cmos_post_extra(u32 value) { - if (!CONFIG(CMOS_POST_EXTRA)) - return; - spin_lock(&cmos_post_lock);
switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38191 )
Change subject: drivers/pc80/rtc: Drop CMOS_POST_EXTRA option ......................................................................
Patch Set 4: Code-Review+1
I wonder what this `extra` is good for
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38191 )
Change subject: drivers/pc80/rtc: Drop CMOS_POST_EXTRA option ......................................................................
Patch Set 5: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38191 )
Change subject: drivers/pc80/rtc: Drop CMOS_POST_EXTRA option ......................................................................
Patch Set 5: Code-Review+2
Hello build bot (Jenkins), Furquan Shaikh, Angel Pons, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38191
to look at the new patch set (#9).
Change subject: drivers/pc80/rtc: Drop CMOS_POST_EXTRA option ......................................................................
drivers/pc80/rtc: Drop CMOS_POST_EXTRA option
Change-Id: I379a5664776624600ff1c2919bffa77c877d87ab Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M configs/config.google_meep_cros M configs/config.google_reef_cros M src/console/Kconfig M src/drivers/elog/elog.c M src/drivers/pc80/rtc/post.c 5 files changed, 4 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/38191/9
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38191 )
Change subject: drivers/pc80/rtc: Drop CMOS_POST_EXTRA option ......................................................................
Patch Set 9: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38191 )
Change subject: drivers/pc80/rtc: Drop CMOS_POST_EXTRA option ......................................................................
drivers/pc80/rtc: Drop CMOS_POST_EXTRA option
Change-Id: I379a5664776624600ff1c2919bffa77c877d87ab Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38191 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M configs/config.google_meep_cros M configs/config.google_reef_cros M src/console/Kconfig M src/drivers/elog/elog.c M src/drivers/pc80/rtc/post.c 5 files changed, 4 insertions(+), 22 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/configs/config.google_meep_cros b/configs/config.google_meep_cros index f87b02b..9911614 100644 --- a/configs/config.google_meep_cros +++ b/configs/config.google_meep_cros @@ -14,7 +14,6 @@
# Event Logging CONFIG_CMOS_POST=y -CONFIG_CMOS_POST_EXTRA=y CONFIG_CMOS_POST_OFFSET=0x70 CONFIG_COLLECT_TIMESTAMPS=y CONFIG_ELOG=y diff --git a/configs/config.google_reef_cros b/configs/config.google_reef_cros index 9bbb3b3..6dcda44 100644 --- a/configs/config.google_reef_cros +++ b/configs/config.google_reef_cros @@ -10,5 +10,4 @@ # CONFIG_CONSOLE_SERIAL is not set CONFIG_CMOS_POST=y CONFIG_CMOS_POST_OFFSET=0x70 -CONFIG_CMOS_POST_EXTRA=y CONFIG_PAYLOAD_NONE=y diff --git a/src/console/Kconfig b/src/console/Kconfig index b893698..7c6e9bc 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -392,14 +392,6 @@ If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value defined in the mainboard option table.
-config CMOS_POST_EXTRA - bool "Store extra logging info into CMOS" - depends on CMOS_POST - default n - help - This will enable extra logging of work that happens between post - codes into CMOS for debug. This uses an additional 8 bytes of CMOS. - config CONSOLE_POST bool "Show POST codes on the debug console" depends on !NO_POST diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index ca604dd..1d4b135 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -765,7 +765,6 @@ "in previous boot: 0x%02x/0x%04x\n", code, extra);
elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); - /* Always zero with !CMOS_POST_EXTRA. */ if (extra) elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); #endif diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c index 5bee5be..41a664e 100644 --- a/src/drivers/pc80/rtc/post.c +++ b/src/drivers/pc80/rtc/post.c @@ -20,13 +20,11 @@ switch (cmos_read(CMOS_POST_BANK_OFFSET)) { case CMOS_POST_BANK_0_MAGIC: *code = cmos_read(CMOS_POST_BANK_1_OFFSET); - if (CONFIG(CMOS_POST_EXTRA)) - *extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); + *extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); break; case CMOS_POST_BANK_1_MAGIC: *code = cmos_read(CMOS_POST_BANK_0_OFFSET); - if (CONFIG(CMOS_POST_EXTRA)) - *extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); + *extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); break; }
@@ -61,10 +59,8 @@ /* Initialize to zero */ cmos_write(0, CMOS_POST_BANK_0_OFFSET); cmos_write(0, CMOS_POST_BANK_1_OFFSET); - if (CONFIG(CMOS_POST_EXTRA)) { - cmos_write32(0, CMOS_POST_BANK_0_EXTRA); - cmos_write32(0, CMOS_POST_BANK_1_EXTRA); - } + cmos_write32(0, CMOS_POST_BANK_0_EXTRA); + cmos_write32(0, CMOS_POST_BANK_1_EXTRA); }
cmos_write(magic, CMOS_POST_BANK_OFFSET); @@ -88,9 +84,6 @@
void cmos_post_extra(u32 value) { - if (!CONFIG(CMOS_POST_EXTRA)) - return; - spin_lock(&cmos_post_lock);
switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
-
Aaron Durbin (Code Review) -
Angel Pons (Code Review)
-
Furquan Shaikh (Code Review)
-
Kyösti Mälkki (Code Review)
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Patrick Georgi (Code Review)