Change in coreboot[master]: soc/intel/common: Enable rom cache on all CPU threads

[Kane Chen (Code Review)]

Attention is currently required from: Arthur Heymans, Subrata Banik.
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63486 )

Change subject: soc/intel/common: Enable rom cache on all CPU threads
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Patch Set 3:

(1 comment)

Patchset:

PS2:
> > > > > > ah yes, thanks for capturing this. […]

I'm not sure if i get Arthur's question.

The issue is when bsp asks all threads to run _x86_setup_mtrrs.
BSP won't wait all threads to be finished. BSP (core 0 Thread0) just keeps exe post_cpus_add_romcache.

And then Core 0 thread 1, finally finishes _x86_setup_mtrrs, but it's after post_cpus_add_romcache run by BSP Core 0 thread 0. 
the mtrr is share btwn Core 0 thread 0 and Core 0 thread 1.

So eventually post_cpus_add_romcache doesn't work as expect and spi address are not actually put in var mtrr since _x86_setup_mtrrs run by Core 0 thread 1 overwrite everything again.

thanks.