[M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts

[Harsha B R (Code Review)]

Attention is currently required from: Tarun Tuli, Jamie Ryu, Wonkyu Kim, Tim Wawrzynczak, Ravishankar Sarawadi, Kapil Porwal, Angel Pons, Nick Vaccaro, Raj Astekar.

Harsha B R has uploaded a new patch set (#2) to the change originally created by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/66190 )

Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
......................................................................

mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts

This patch adds initial romstage code and spd data for DDR5 memory
parts for MTL-RVP. This also configures memory based on the board id.

BUG=b:224325352
TEST=FW_NAME=mtlrvp_p emerge-rex coreboot chromeos-bootimage

Signed-off-by: Jamie Ryu 
Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58
---
M src/mainboard/intel/mtlrvp/Kconfig
M src/mainboard/intel/mtlrvp/Makefile.inc
A src/mainboard/intel/mtlrvp/romstage_fsp_params.c
A src/mainboard/intel/mtlrvp/spd/Makefile.inc
A src/mainboard/intel/mtlrvp/spd/empty.spd.hex
A src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/Makefile.inc
A src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/memory.c
7 files changed, 156 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/66190/2