Change in coreboot[master]: soc/cavium/cn81xx: Set cntfrq_el0

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25450

Change subject: soc/cavium/cn81xx: Set cntfrq_el0
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soc/cavium/cn81xx: Set cntfrq_el0

Set cntfrq_el0 to provide correct timer frequency.

Change-Id: I4b6d0b0cf646a066fc5a51552a1891eccbd91e5e
Signed-off-by: Patrick Rudolph 
---
M src/mainboard/cavium/cn8100_sff_evb/mainboard.c
M src/soc/cavium/cn81xx/include/soc/timer.h
M src/soc/cavium/cn81xx/timer.c
3 files changed, 16 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/25450/1

diff --git a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c
index 0887cde..d9df011 100644
--- a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c
+++ b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c
@@ -19,6 +19,7 @@
 #include <console/console.h>
 #include <soc/clock.h>
 #include <soc/gpio.h>
+#include <soc/timer.h>

static void mainboard_print_info(void)
 {
@@ -70,6 +71,9 @@
    	if (!uart_is_enabled(i))
    		uart_setup(i, 0);
    }
+
+	/* Init timer */
+	soc_timer_init();
 }

static void mainboard_enable(device_t dev)
diff --git a/src/soc/cavium/cn81xx/include/soc/timer.h b/src/soc/cavium/cn81xx/include/soc/timer.h
index 6d48831..f9e5961 100644
--- a/src/soc/cavium/cn81xx/include/soc/timer.h
+++ b/src/soc/cavium/cn81xx/include/soc/timer.h
@@ -17,4 +17,7 @@
 void watchdog_disable(const size_t index);
 int watchdog_is_running(const size_t index);

+/* Timer functions */
+void soc_timer_init(void);
+
 #endif	/* __SOC_CAVIUM_CN81XX_TIMER_H__ */
diff --git a/src/soc/cavium/cn81xx/timer.c b/src/soc/cavium/cn81xx/timer.c
index ee8d639..ab8391b 100644
--- a/src/soc/cavium/cn81xx/timer.c
+++ b/src/soc/cavium/cn81xx/timer.c
@@ -17,6 +17,7 @@
 #include <timer.h>
 #include <soc/addressmap.h>
 #include <assert.h>
+#include <arch/clock.h>

/* Global System Timers Unit (GTI) registers */
 struct cn81xx_timer {
@@ -89,6 +90,9 @@
    mono_time_set_usecs(mt, timer_raw_value());
 }

+/* Setup counter to operate at 1MHz */
+static const size_t tickrate = 1000000;
+
 /**
  * Init Global System Timers Unit (GTI).
  * Configure timer to run at 1MHz tick-rate.
@@ -106,8 +110,6 @@
    /* Use coprocessor clock source */
    write32(&gti->cc_imp_ctl, 0);

-	/* Setup counter to operate at 1MHz */
-	const size_t tickrate = 1000000;
    write32(&gti->cc_cntfid0, tickrate);
    write32(&gti->ctl_cntfrq, tickrate);
    write32(&gti->cc_cntrate, ((1ULL << 32) * tickrate) / sclk);
@@ -119,6 +121,11 @@
    //BDK_MSR(CNTPS_CTL_EL1, u);
 }

+void soc_timer_init(void)
+{
+	set_cntfrq(tickrate);
+}
+
 /**
  * Setup the watchdog to expire in timeout_ms milliseconds. When the watchdog
  * expires, the chip three things happen: