[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock

[Subrata Banik (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Saurabh Mishra, Tarun.

Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
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Patch Set 30:

(8 comments)

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83354/comment/f5eb8305_af247d34?usp... :
PS30, Line 141: 0xfe02c000
what is the reason behind changing the UART base address ?

File src/soc/intel/pantherlake/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/884e4381_ab964f02?usp... :
PS30, Line 17: 
```
/* System Agent Fabric (SAF) */
```

https://review.coreboot.org/c/coreboot/+/83354/comment/767e58c3_55b9b0ea?usp... :
PS30, Line 18:         
use tab

https://review.coreboot.org/c/coreboot/+/83354/comment/00df8362_a132c470?usp... :
PS30, Line 18: 0xfa000000
as per FAS "SAFBAR will be moved to above 4GB", I could see the BAR is above 4GB as per FAS

https://review.coreboot.org/c/coreboot/+/83354/comment/42be9ae7_65df5112?usp... :
PS30, Line 19:            
same

https://review.coreboot.org/c/coreboot/+/83354/comment/b10c341f_d0d5a80c?usp... :
PS30, Line 46:      
use tab

File src/soc/intel/pantherlake/include/soc/pcr_ids.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/2953dbea_2c765bc6?usp... :
PS30, Line 6: ids
IDs?

File src/soc/intel/pantherlake/include/soc/pm.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/f1bed429_8751b925?usp... :
PS30, Line 7: WAK_STS		BIT(15)
            : #define  PCIEXPWAK_STS		BIT(14)
            : #define  PRBTNOR_STS		BIT(11)
            : #define  RTC_STS		BIT(10)
            : #define  PWRBTN_STS		BIT(8)
            : #define  GBL_STS		BIT(5)
            : #define  BM_STS			BIT(4)
            : #define  TMROF_STS		BIT(0)
use one space to start with because these are the bit fields of PM1_STS

same for rest of the macros